ADVANCE INFORMATION
VCT 38xxA
amplitude, the external controller reads this register,
calculates the vertical scaling coefficient and transfers
the new settings, e.g. vertical sawtooth parameters,
horizontal scaling coefficient etc., to the VCT 38xxA.
sures the falling edge of sync, as well as the integrated
sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it
thus counts synchronously to the video signal.
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are pro-
cessed as non-black lines. Therefore, the subtitles are
visible on the screen. To suppress the subtitles, the
vertical zoom coefficient is calculated by selecting the
larger number of black lines only. Dark video scenes
with a low contrast level compared to the letterbox area
are indicated by the BLKPIC bit.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/mini-
mum of the video signal. This information is processed
by the FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is
integrated. The FP uses the integrator value to derive
vertical sync and field information.
2.7. Test Pattern Generator
The information extracted by the video sync process-
ing is multiplexed onto the hardware front sync signal
(FSY) and is distributed to the rest of the video pro-
cessing system.
The YCrCb outputs can be switched to a test mode
where YCrCb data are generated digitally in the
VCT 38xxA. Test patterns include luma/chroma ramps
and flat fields.
The data for the vertical deflection, the sawtooth, and
the East-West correction signal is calculated by the
VCT 38xxA. The data is buffered in a FIFO and trans-
ferred to the back-end by a single wire interface.
2.8. Video Sync Processing
Fig. 2–10 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase low-pass filter eliminates
all noise and video contents above 1 MHz. The sync is
separated by a slicer; the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator mea-
Frequency and phase characteristics of the analog
video signal are derived from PLL1. The results are fed
to the scaler unit for data interpolation and orthogonal-
ization and to the clock synthesizer for line-locked
clock generation. Horizontal and vertical syncs are
latched with the line-locked clock.
PLL1
low-pass
1 MHz
&
Phase
Separator
&
Front Sync
Front
Horizontal
Sync
Separation
Skew
Sync
counter
Generator
Vblank
Field
sync slicer
Low-pass
video
input
Clock
Synthesizer
Syncs
Front-end
Timing
Clock
H/V Syncs
Clamp &
Signal
Meas.
clamping, colorkey, FIFO_write
Sawtooth
Vertical
Vertical
Sync
Separation
Vertical
Serial
Data
Parabola
FIFO
E/W
Sawtooth
Calculation
Fig. 2–10: Sync separation block diagram
Micronas
17
MICRONAS [ MICRONAS ]
