VCT 38xxA
ADVANCE INFORMATION
6.7.3.8. Analog Video Front-End and A/D Converters
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Luma – Path (Composite)
R
Input Resistance
VIN1−4
1
–
–
MΩ
Code Clamp–DAC=0
VIN
C
Input Capacitance
–
5
–
pF
VIN
VIN
VIN
V
V
Full Scale Input Voltage
Full Scale Input Voltage
AGC step width
1.8
0.5
–
2.0
0.6
0.166
–
2.2
0.7
–
V
V
min. AGC Gain
PP
PP
max. AGC Gain
AGC
DNL
dB
LSB
V
6-Bit Resolution= 64 Steps
f
=1MHz,
sig
– 2 dBr of max. AGC–Gain
AGC Differential Non-Linearity
Input Clamping Level, CVBS
–
±0.5
–
AGC
VINCL
V
–
1.0
Binary Level = 64 LSB
min. AGC Gain
Q
Clamping DAC Resolution
–16
0.7
–
−
15
steps
µA
5 Bit – I–DAC, bipolar
CL
V
=1.5 V
VIN
I
Input Clamping Current per step
1.0
–
1.3
±0.5
CL–LSB
DNL
Clamping DAC Differential Non-
Linearity
LSB
ICL
Chroma – Path (Composite)
R
Input Resistance
SVHS Chroma
CIN1
CIN2
1.4
2.0
2.6
kΩ
CIN
V
V
Full Scale Input Voltage, Chroma
1.08
1.2
1.5
1.32
V
V
CIN
PP
Input Bias Level,
SVHS Chroma
−
−
CINDC
Binary Code for Open
Chroma Input
−
128
−
−
Chroma – Path (Component)
R
C
Input Resistance
CRIN
CBIN
1
−
−
MΩ
Code Clamp–DAC=0
CIN
Input Capacitance
−
−
4.5
0.92
1.32
−
pF
CIN
V
V
V
Full Scale Input Voltage
Full Scale Input Voltage
0.76
1.08
−
0,84
1.2
1.5
−
V
V
V
minimal Range
CIN
PP
PP
extended Range
CIN
Input Clamping Level C , C
Binary Level = 128 LSB
6 Bit – I–DAC, bipolar
CINCL
r
b
Q
Clamping DAC Resolution
–32
0.59
−
31
steps
µA
CL
V
=1.5 V
VIN
I
Input Clamping Current per step
0.85
−
1.11
±0.5
CL–LSB
DNL
Clamping DAC Differential Non-
Linearity
LSB
ICL
156
Micronas
MICRONAS [ MICRONAS ]
