VCT 38xxA
ADVANCE INFORMATION
5. TV Controller
5.1. Introduction
5.2.1. CPU Slow Mode
The TV controller basically consists of the CPU, RAM,
ROM, and a number of peripheral modules.
To reduce power consumption considerably, the user
can reduce the internal CPU clock frequency to 1/256
of the normal fCPU value. In this CPU Slow mode, pro-
gram execution is reduced to 1/256 of the normal
speed, but clocking of most other modules remains
unaffected. The modules that are affected by CPU
Slow mode are:
For instance:
– a memory banking module is included to allow
access to more than 64 kB memory.
– a bootloader software is included to allow in-system-
downloading of external code to Flash memory via
the I2C interface.
1. CPU and Interrupt Controller with all internal and
external interrupts
2. RAM, ROM and DMA
3. Watchdog
The TV controller runs the complete software neces-
sary to control a TV set. The software includes control
of the audio, video, OSD, and text processors on chip,
as well, as control of external devices like tuner or ste-
reo decoder.
Some modules must not be operated during CPU Slow
mode. Refer to module sections for details.
After reset the CPU is in Fast mode (fCPU = fOSC).
Communication between the TV controller and exter-
nal devices is done either via I2C bus interface or via
programmable port pins.
CPU Slow mode is enabled by clearing flag CPUFST
in standby register SR1. The CPU clock frequency
reduction to fOSC/256 will take effect after a maximum
delay of 256 fOSC periods.
The TV Controller is clocked with fOSC = fXTAL/2.
Returning CPU to Fast mode is done by setting flag
CPUFST to High. The CPU clock frequency will imme-
diately change to its normal fOSC value.
5.2. CPU
The CPU is fully compatible to WDC’s W65C02 micro-
processor. The processor has 8-bit registers/accumu-
lator, an 8-bit data bus, and a 16-bit address bus. For
further information about the CPU core, please refer to
the WDC W65C02 data sheet.
Fig. 5–1 shows the memory access signals during
CPU fast and slow mode.
fast mode
slow mode
fOSC
PH2
CCUPH2
RW
WE
OE
Fig. 5–1: Memory access signals
86
Micronas
MICRONAS [ MICRONAS ]
