VCT 38xxA
ADVANCE INFORMATION
5.11.4.Patch Operation
5.11.5.Patch Registers
To activate a number of properly initialized patch cells
for ROM code patching, set all the corresponding
PSEL bits in registers PER1, then PER0, setting bit
PER0.PMEN to 1.
160: 1E64
161: PAR0
162: Patch Address Register 0
bit
7
PA7
1
6
5
PA5
1
4
PA4
1
3
PA3
1
2
PA2
1
1
PA1
1
0
PA0
1
w
PA6
The Memory Patch Module will immediately start com-
paring the current address to the setting of the enabled
patch cells. In case of a match, the ROM data will be
replaced by the corresponding patch cell data register
setting.
reset
1
163: 1E65
164: PAR1
165: Patch Address Register 1
bit
w
7
PA15
1
6
PA14
1
5
PA13
1
4
PA12
1
3
PA11
1
2
PA10
1
1
PA9
1
0
PA8
1
To reconfigure the Memory Patch Module, first set
PER0.PMEN to 0. The module will immediately termi-
nate patch operation.
reset
.
166: 1E66
167: PAR2
168: Patch Address Register 2
PH2
bit
w
7
6
5
4
3
2
1
0
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
A1
A2
A3
A2
A3
ADB[23:0]
reset
1
1
1
1
1
1
1
1
D1
D2
PD1
D3
PD2
DB[7:0]
RDY
169: 1E67
170: PDR
171: Patch Data Register
bit
w
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
reset
PATOE
0
0
0
0
0
0
0
0
ROMEN
172: 1E68
173: PER0
174: Patch Enable Register 0
Fig. 5–17: Patch timing
bit
w
7
6
5
4
3
2
1
0
PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
PMEN
reset
0
0
0
0
0
0
0
0
175: 1E69
176: PER1
177: Patch Enable Register 1
bit
w
7
x
x
6
x
x
5
x
x
4
x
x
3
x
x
2
1
0
PSEL9 PSEL8 PSEL7
reset
0
0
0
PA23 to 0 Patch Address
Upon occurrence of this address the patch cell
replaces ROM data with data from PDR.
PD7 to 0
Patch Data
Data to replace false ROM data at certain address.
PSEL0 to 9 Select Patch Cell
w1:
w0:
select cell for write or enable for patch
disable patch cell
Before writing compare address or replace data of a
patch cell, only one cell must be selected. In compare
mode one or more patch cells can be selected.
PMEN
w1:
w0:
Patch Mode Enable
enable patch mode of all cells
enable write mode of all cells
108
Micronas
MICRONAS [ MICRONAS ]
