VCT 38xxA
ADVANCE INFORMATION
3.14.I2C-Bus Slave Interface
The time required to process the I2C buffer depends
on other processes running inside the TPU firmware.
Thus the following I2C telegram addressing the TPU
can be held after the slave address byte until the old
telegram is completely processed.
Communication between the TPU and the TV control-
ler is done via I2C bus. For detailed information on the
I2C bus please refer to the Philips manual ‘I2C bus
Specification’.
The TPU acts as a slave transmitter/receiver and uses
clock synchronization to slow down the data transfer if
necessary. General call address will not be acknowl-
edged.
3.14.1.Subaddressing
Access to all memory locations and to the command
interface is achieved by subaddressing. Both the exter-
nal DRAM and the internal CPU memory can be
addressed completely. The TPU acknowledges 6 dif-
ferent subaddresses following the slave address (see
Table 3–17 on page 82).
Different memories and functions of TPU can be
accessed by subaddressing. The byte following the
slave address byte is defined as the subaddress byte.
Maximum length of an I2C telegram is 256 Bytes fol-
lowing slave address and subaddress byte. The inter-
face supports data transfer with autoincrement.
The following symbols are used to describe the I2C
example telegrams:
<
>
start condition
stop condition
address bank byte
address high byte
address low byte
command byte
data byte
status byte
0 − n continuation bytes
The I2C bus interface is interrupt-driven and uses an
internal 48-Byte buffer to collect I2C data in real-time
without disturbing internal processes. This is done to
avoid clock synchronization as far as possible. When
the TPU has to process the I2C buffer and the I2C tele-
gram has not yet been stopped, the I2C clock line will
be held down.
ab
ah
al
cc
dd
ss
..
Table 3–17: I2C bus subaddresses
Name
TPU
Binary Value
0010 001x
0111 1000
0111 1001
0111 1010
0111 1011
0111 1100
0111 1101
Hex Value
Mode
W, R
W
Function
22, 23
78
TPU slave address
Sub 1
Sub 2
Sub 3
Sub 4
Data
subaddressing CPU (static)
79
W
subaddressing CPU (autoincrement)
subaddressing DRAM (autoincrement)
subaddressing command language
subaddressing data register
7A
W
7B
W
7C
R/W
R
Status
7D
status register
bit 7 = command wait
bit 6 = command invalid
bit 5 = command found no data
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = 0
bit 0 = 0
3.14.1.1. CPU Subaddressing
page 76). The static CPU subaddress can be used to
write more than 1 Byte into the same I/O page register.
There are 2 CPU subaddresses to access CPU mem-
ory: either with static memory address or with autoin-
crementing memory address. The main purpose of
CPU subaddressing is to write text into the OSD buffer
and to access the I/O page (see Section 3.13. on
The CPU subaddress has to be followed by 2 address
bytes defining the CPU memory address. The follow-
ing data byte is written into this address. In the case of
autoincrement the continuation bytes are written into
incrementing memory addresses.
82
Micronas
MICRONAS [ MICRONAS ]
