VCT 38xxA
ADVANCE INFORMATION
3.13.I/O Register
Most hardware-related functions of the TPU are con-
trolled by memory mapped I/O of the 65C02. The
application software has access to the I/O registers via
I2C bus using the CPU subaddresses SUB1 and SUB2
(see Section 3.14.1.1. on page 82).
Most of the I/O registers can only be written and will
not return useful data when read by application soft-
ware. Reset values are written by TPU during initializa-
tion.
Note:
For compatibility reasons, every undefined bit of a
write register should be set to ‘0’. Undefined bits of
a read register should be treated as “don’t care”.
0200 H
Bit
R/W
CONTROL REGISTER
Reset
00 H
Write Function
Read Function
all
During reset the control register is loaded with the contents of the address FFF9H, but it can be read and
written via software.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1 = CPU disable
0 = CPU enable
1 = program RAM disable
0 = program RAM enable
1 = program ROM disable
0 = program ROM enable
1 = character ROM disable
0 = character ROM enable
1 = DMA interface disable
0 = DMA interface enable
1 = I/O page disable
0 = I/O page enable
1 = test mode on
0 = test mode off
1 = burnin test mode (only if test pin high)
0 = normal test mode
1 = burnin test mode
0 = normal test mode
0202 H
Write
Reset
0
STANDBY
Bit
2
Function
1 = digital circuitry power off(CPU still active with slow clock)
0 = digital circuitry power on
1
0
1 = analog front-end power off
0 = analog front-end power on
0213 H
Write
Reset
0
INTERFACE MODE
Bit
1
Function
1 = standby enable
0 = standby disable
(if bit 2 of register 0202H = 1)
0251 H
Bit
Write
Reset
07 H
BLANKING STOP
Function
all
horizontal stop of blanking pulse in character increments
correct blanking pulse cannot be guaranteed if blanking start = blanking stop
76
Micronas
MICRONAS [ MICRONAS ]
