ADVANCE INFORMATION
VCT 38xxA
3.5. Teletext Page Management
0000
Zero Page
As a state-of-the-art teletext decoder, the TPU is able
to store and manage a sufficient number of teletext
pages to absorb the annoying transmission cycle
times. The number of available pages is only limited by
the memory size. With an intelligent software and a
4-Mbit SRAM it is possible to store and to control more
than 500 teletext pages.
Stack Page
I/O Page
Extra Page
1000
8000
The management of such a data base is a typical soft-
ware task and is therefore performed by the 65C02.
Using a fixed length page table with one entry for every
possible page, the software distributes the content of
the acquisition scratch buffer among the page memory.
The page size is fixed to 1 kByte, only ghost rows are
chained in 128-Byte segments to avoid unused mem-
ory space.
12K
Character ROM
D000
12K
Program ROM
A stored teletext page cannot be displayed directly,
because of the row-adaptive transmission and the
level 2 enhancements (row 26−29). Therefore, the
CPU has to transfer the selected teletext page into a
display page buffer, adding extra data such as charac-
ter set extension and non-spacing attributes.
DMA
Interface
ADR
DATA
DATA
ADR
BE
RDY
3.5.1. Memory Manager
65C02
Display
BUSREQ
The Memory manager is the core of the internal TPU
firmware. Most of the acquisition and display related
functions are controlled by this management.
Fig. 3–2: Memory environment of text controller
3.4. Teletext Acquisition
Acquisition
The only task of the slicer circuit is to extract teletext
lines from the incoming composite video signal and to
store them into the acquisition scratch buffer of the
internal/external SRAM. No page selection is done at
this hardware level.
Scratch
Memory
Four analog sources can be connected, thus it is pos-
sible to receive text from one channel while watching
another on the screen. After clamping and AGC ampli-
fier the analog video signal is converted into binary
data. Sync separation is done by a sync slicer and a
horizontal PLL, which generate the horizontal and ver-
tical timing. By these means, no external sync signals
are needed and any available signal source can be
used for teletext reception.
Page
Table
Memory
Manager
Page
Memory
Display
Memory
The teletext information itself is acquired using adap-
tive slicers on bit and byte level with soft error detec-
tion to decrease the bit error rate under bad reception
conditions. The slicer can be programmed to different
bit rates for reception of PAL, NTSC or MAC world sys-
tem teletext as well as VPS, WSS, or CAPTION sig-
nals.
Display
Controller
Fig. 3–3: Memory Manager
Micronas
49
MICRONAS [ MICRONAS ]
