VCT 38xxA
ADVANCE INFORMATION
Contents, continued
Page
Section
Title
85
4.
Audio Processing
85
85
85
85
4.1.
4.2.
4.3.
4.4.
Introduction
Input Select
Volume Control
I2C-Bus Slave Interface
86
5.
TV Controller
86
5.1.
Introduction
86
86
5.2.
5.2.1.
CPU
CPU Slow Mode
87
87
87
5.3.
5.3.1.
5.3.2.
RAM and ROM
Address Map
Bootloader
87
89
90
5.4.
5.5.
5.6.
Control Register
Standby Registers
Test Registers
90
90
90
91
5.7.
Reset Logic
5.7.1.
5.7.2.
5.7.2.1.
Alarm Function
Software Reset
From Standby into Normal Mode
91
91
92
92
93
94
94
94
5.7.2.2.
5.7.3.
5.7.3.1.
5.7.3.2.
5.7.3.3.
5.7.4.
From Normal into Standby Mode
Internal Reset Sources
Supply Supervision
Clock Supervision
Watchdog
External Reset Sources
Summary of Module Reset States
Reset Registers
5.7.5.
5.7.6.
95
95
5.8.
5.8.1.
Memory Banking
Banking Register
96
98
5.9.
5.9.1.
DMA Interface
DMA Registers
99
99
99
99
99
5.10.
Interrupt Controller
Features
General
Initialization
Operation
Inactivation
Precautions
Interrupt Registers
Interrupt Assignment
Interrupt Multiplexer
5.10.1.
5.10.2.
5.10.3.
5.10.4.
5.10.5.
5.10.6.
5.10.7.
5.10.8.
5.10.8.1.
99
101
101
103
103
104
106
5.10.9.
5.10.10.
Port Interrupt Module
Interrupt Timing
107
107
107
107
108
108
5.11.
Memory Patch Module
Features
General
Initialization
Patch Operation
Patch Registers
5.11.1.
5.11.2.
5.11.3.
5.11.4.
5.11.5.
109
111
5.12.
5.12.1.
I2C-Bus Master Interface
I2C Bus Master Interface Registers
4
Micronas
MICRONAS [ MICRONAS ]
