ADVANCE INFORMATION
VCT 38xxA
5.10.Interrupt Controller
operates with the new vector of the interrupt service
routine.
The Interrupt Controller has 16 input channels (see
Fig. 5–10 on page 100). Each input has its own inter-
rupt vector pointing to an interrupt service routine
(ISR). One of 15 priority levels can be assigned to
each input or the input can be disabled. The Interrupt
Controller is connected to the NMI input of the CPU.
But despite of the non-maskable interrupt input, it is
possible to disable all interrupt sources in total in the
Interrupt Controller.
When the Interrupt Controller writes the new vector to
the address bus, the interrupt pending flag of this vec-
tor is set, indicating that no interrupt is pending.
The software must pull the top entry from the priority
stack at the end of an interrupt service routine. This
happens with the write access to the interrupt return
register IRRET. Then the next entry (with lower prior-
ity) is visible at top of stack and is compared with the
priority latch.
5.10.1.Features
The Interrupt Controller and related circuitry is clocked
by the CPU clock and participates in CPU Fast and
Slow mode.
– 16 interrupt inputs.
– 16 interrupt vectors.
– 15 individual priority levels.
– Global/individual disable of interrupts.
– Single interrupt service mode.
5.10.3.Initialization
After reset, all internal registers are cleared but the
Interrupt Controller is active. When an interrupt
request arrives, it will be stored in the respective pend-
ing register IRP/IRRET. But it will not trigger an inter-
rupt as long as its interrupt priority register IRPRIxy is
set to zero.
5.10.2.General
Interrupt requests are served in the order of their pro-
grammed priority level. Interrupt requests of the same
priority level are served in descending order of inter-
rupt input number.
Proper SW configuration of the interrupt sources in
peripheral modules has to be made prior to operation.
Each of the 16 interrupt inputs clears a flag in the inter-
rupt pending register (IRRET and IRP), which can be
read by the user. A pending interrupt enables the out-
put of the corresponding priority register (IRPRI10 to
IRPRIFE) which is connected to a parallel priority
decoder together with the other priority registers. The
decoder outputs the highest priority and its input num-
ber to a latch. The latched priority is compared with the
top entry of the priority stack. The top entry of the pri-
ority stack contains the priority of the actual served
interrupt. Lower entries contain interrupts with lower
priority whose interrupt service routines were started
but interrupted by the higher priority interrupts above. If
the latched priority is lower or equal than the top of
stack priority, nothing happens. If the latched priority is
higher than the top of stack priority, a NMI is sent to the
CPU and the latched priority is pushed on the stack.
Before enabling individual inputs, make sure that no
previously received signal on that input has cleared its
pending flag which may trigger the Interrupt Controller.
Clear all pending interrupts with the flag IRC.CLEAR to
avoid such an effect.
5.10.4.Operation
Activation of an interrupt input is done by writing a pri-
ority value ranging from 1h to Fh to the respective
IRPRIxy register. Upon an interrupt request, pending
or fresh, the Interrupt Controller will immediately gen-
erate an interrupt.
During operation, changes in the priority register set-
ting may be made to obtain varying interrupt servicing
strategies.
Flags IRC.DAINT,
IRC.DINT and
The Interrupt Controller signals an interrupt by NMI
input to the CPU. After the current instruction is fin-
ished the CPU starts an interrupt sequence. First it
puts the program bank register, the program counter
High byte, the program counter Low byte and the pro-
gram status register to the stack. Then the CPU writes
the vector address Low byte (00FFFAh) to the bus.
The Interrupt Controller recognizes this address and
stops the CPU by the RDY signal. Now the Interrupt
Controller writes the vector address Low and High byte
of the corresponding interrupt number to the bus and
releases the CPU by releasing RDY. The CPU now
IRC.A1INT allow some variation in the Interrupt Con-
troller response behavior.
5.10.5.Inactivation
There are two possibilities to disable an interrupt within
the Interrupt Controller. Changing the priority of an
interrupt input to zero disables this interrupt locally.
Interrupts are globally disabled by writing a zero to flag
IRC.DINT of register IRC.
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