ADVANCE INFORMATION
VCT 38xxA
5.16.Tuning Voltage Pulse Width Modulator
5.16.1.Features
– 14bit resolution
– standby mode
The Tuning Voltage Pulse Width Modulator (TVPWM),
in combination with an external low pass filter, serves
as a digital to analog converter to control voltage syn-
thesis tuning. It can also be operated as a normal 8-bit
PWM.
0
TVPWM
Interrupt
Source
load
clk
fOSC/21
8 bit PWM Counter
6 bit Frame Counter
1
8
6
SR0.TVPWM
Comparator
Extension Logic
8
6
w
TVPWMH Register
TVPWML Register
pulse
pwm
TVPWM
≥1
Fig. 5–2: Block Diagram of 14bit Tuning Voltage PWM
5.16.2.General
An interrupt is generated after completion of a frame of
64 reload cycles. The interrupt source output of this
module is routed to the Interrupt Controller logic (see
Section 5.10. on page 99).
The TVPWM is based on an 8-bit PWM built by a
counter and a programmable comparator (see Fig. 5–
2). The overflow of the counter reloads the comparator
with the content of the TVPWMH register and sets the
TVPWM output to High. Matching the counter value,
the comparator sets the TVPWM output to Low. The
counter is continually running, producing PWM cycles
with a length of 256 T.
The TVPWM is not affected by CPU Slow mode. It is
recommended that the CPU should not write the
TVPWM registers during Slow mode.
Depending on the content of the TVPWML register, the
6-bit pulse extension logic will add additional single
clock pulses distributed over a frame of 64 reload
cycles (see Fig. 5–3). This gives 14-bit resolution
when integrating over a complete frame. The frame
rate is 309 Hz, the frame period is 3.24 ms.
1 T
cycle n+1
256 T
cycle n
256 T
Fig. 5–3: TVPWM Timing
Micronas
121
MICRONAS [ MICRONAS ]
