ADVANCE INFORMATION
VCT 38xxA
5.12.1.I2C Bus Master Interface Registers
1T
178: 1FD0
179: I2CWS0
180: I2C Write Start Register 0
SDA
bit
7
6
5
4
3
2
1
0
0
w
I2C Address
reset
0
0
0
0
0
0
0
SCL
Writing this register moves I2C start condition, I2C
Address and ACK=1 into the Write FIFO.
1/2T
1T
1/4T
Fig. 5–19: Start condition I2C bus
181: 1FD1
182: I2CWS1
183: I2C Write Start Register 1
bit
7
6
5
4
3
2
1
0
0
w
I2C Address
reset
0
0
0
0
0
0
0
1T
Writing this register moves I2C start condition, I2C
Address and ACK=0 into the Write FIFO.
SDA
repeated
8 times
SCL
184: 1FD2
185: I2CWD0
186: I2C Write Data Register 0
bit
7
6
5
4
0
3
2
1
0
0
w
I2C Data
1/4T 1/2T 1/4T
reset
0
0
0
0
0
0
Writing this register moves I2C Data and ACK=1 into
the Write FIFO.
Fig. 5–20: Single bit on I2C bus
187: 1FD3
188: I2CWD1
189: I2C Write Data Register 1
bit
7
6
5
4
0
3
2
1
0
0
w
I2C Data
SDA
SCL
reset
0
0
0
0
0
0
Writing this register moves I2C Data and ACK=0 into
the Write FIFO.
1/4T
3/4T
190: 1FD4
191: I2CWP0
192: I2C Write Stop Register 0
Fig. 5–21: Stop condition I2C bus
bit
7
6
5
4
0
3
2
1
0
0
w
I2C Data
reset
0
0
0
0
0
0
Writing this register moves I2C Data, ACK=1 and I2C
stop condition into the Write FIFO.
193: 1FD5
194: I2CWP1
195: I2C Write Stop Register 1
bit
7
6
5
4
0
3
2
1
0
0
w
I2C Data
reset
0
0
0
0
0
0
Writing this register moves I2C Data, ACK=0 and I2C
stop condition into the Write FIFO.
Micronas
111
MICRONAS [ MICRONAS ]
