VCT 38xxA
ADVANCE INFORMATION
5.10.10.Interrupt Timing
Evaluation needs one clock cycle until the Interrupt
Controller pulls the signal NMI Low.
The interrupt response time is calculated from the
interrupt event up to the first interrupt vector on the
address bus (see Fig. 5–15 on page 106).
After the falling edge of NMI the CPU finishes the
actual command. If the falling edge of NMI happens
one clock cycle before an opcode fetch, the following
command will be finished too. Then PC and status will
be saved on stack before the Low byte of the interrupt
vector is written to the address bus.
After an interrupt event, the Interrupt Controller starts
evaluation with the first falling edge of PH2.
Interrupt
Finish actual command and save status.
(Save status = 5 clocks).
PH2
Interrupt
Request
NMI
A0...23
RDY
00FFFA
DMA
Vector 1st Byte Vector 2nd Byte Opcode ISR
Clear
Request
Interrupts
enabled
DMAE
Fig. 5–15: Interrupt timing diagram
106
Micronas
MICRONAS [ MICRONAS ]
