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VCT3804A 参数 Datasheet PDF下载

VCT3804A图片预览
型号: VCT3804A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
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ADVANCE INFORMATION  
VCT 38xxA  
2.12.6.Protection Circuitry  
Picture tube and drive stage protection is provided  
through the following measures:  
– Vertical flyback protection input:  
This pin searches for a negative edge in every field,  
otherwise the RGB drive signals are blanked.  
– Drive shutoff during flyback:  
This feature can be selected by software.  
– Safety input pin:  
This input has two thresholds. Between zero and the  
lower threshold, normal functioning takes place.  
Between the lower and the higher threshold, the  
RGB signals are blanked. Above the higher thresh-  
old, the RGB signals are blanked and the horizontal  
drive is shut off. Both thresholds have a small hys-  
teresis.  
Vertical:  
a,b,c,d  
0,1,0,0  
0,1,1,0  
0,1,0,1  
East/West:  
a,b,c,d,e  
0,0,1,0,0  
0,0,0,0,1  
0,0,1,1,1  
Fig. 2–25: Vertical and East/West deflection waveforms  
2.13.Reset Function  
for the digital circuits (VSUPD) goes below ~2.5 V for  
more than 50 ns. This reset signal is extended by  
50 µs after VSUPD is back again.  
Reset of all VDP functions is performed by the RESQ  
pin. When this pin becomes active, all internal regis-  
ters and counters are lost. The TV controller can acti-  
vate the RESQ pin by software (see Section 5.7.2. on  
page 90).  
2.14.Standby and Power-On  
The VDP does not have a standby mode. To disable all  
the analog and digital video functions, it is necessary  
to switch off the supplies for analog front-end  
(VSUPAF), analog back-end (VSUPAB) and digital  
circuitry (VSUPD).  
When the RESQ pin is released, the internal reset is  
still active for 4 µs. After that time, the initialization of  
all required registers is performed by the internal Fast  
Processor. This takes approximately 60 µs. During this  
initialization procedure it is not possible to access the  
VDP via the I2C interface.  
The VDP has clock and voltage supervision circuits to  
generate a stable HOUT signal. The voltage supervi-  
sion activates an internal reset signal when the supply  
Micronas  
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