VCT 38xxA
ADVANCE INFORMATION
WR_Data (subaddress=control info)
Address
Decoder
D0 to D7
WR
0
1
clk = fOSC
Clock Prescaler
Write
half full
empty
FIFO
5 x 11
SR2.I2C
Terminal 1
SDA/SCL
control
2
in
SR
out
Write Logic
Read Logic
2
busy
Terminal 2
P22/P23
P36/P37
Read
FIFO
3 x 8
Start Condition
resets ACK flags
empty
S R
Q
S R
Q
D0 to D7
RD_Data
Status Register
D0 to D7
I2C
Interrupt
RD_Status
Source
Fig. 5–18: Block diagram of I2C bus master interface
110
Micronas