VCT 38xxA
ADVANCE INFORMATION
Table 5–5: Some commonly used settings for address
1: 1F01
2: CR
3: Control Register
location 00FFF9h.
bit
7
6
5
4
3
2
1
0
r/w RESLNG TSTTOG DISEXT
MFM TSTROM IROM
IRAM
ICPU
reset
Value of 00FFF9h
Code
FFh
TEST
Pin
Operation Mode
RESLNG
r/w1:
r/w0:
Reset Pulse Length
Pulse length is 4095/fOSC
Pulse length is 16/fOSC
0
0
1
Stand-alone with internal ROM
or Flash
.
.
DFh
ABh
Emulator mode (CPGA257
package)
This bit specifies the length of the reset pulse which is
output at pin RESQ following an internal reset. If pin
TEST is 1 the first reset after power on is short. The
following resets are as programmed by RESLNG. If pin
TEST is 0 all resets are long.
External program storage con-
nected to Multi Function pins in
Bus mode
TSTTOG
TEST Pin Toggle
r/w1:
Pin TEST can toggle the Multi Function
pins.
Pin TEST can’t toggle the Multi Function
pins.
Table 5–3: TSTROM and IROM usage in mask ROM
parts
r/w0:
TSTROM IROM
selected program storage
internal CPU ROM
This bit is used for test purposes only. If TSTTOG is
true in IC active mode, pin TEST can toggle the Multi
Function pins between Bus mode and normal mode.
1
0
x
1
1
0
internal Test ROM
DISEXT
r/w1:
Disable External Memory Access
external on Multi Function
pins in Bus mode
DB0−DB7, WExQ and OExQ output pins
are tristate during internal memory
access (see Fig. 5–2 on page 89).
r/w0:
DB0−DB7, WExQ and OExQ output pins
are active during internal memory access.
Table 5–4: TSTTOG and MFM usage
TSTTOG
MFM
TEST pin Multi
Function
MFM
r/w1:
r/w0:
Multi Function pin Mode
Enable normal mode.
Enable Test Bus mode.
Pins
x
1
1
0
1
0
0
0
x
1
0
x
normal mode
normal mode
Bus mode
Bus mode
TSTROM Test ROM (mask ROM parts only)
r/w1:
r/w0:
Disable internal Test ROM.
Enable internal Test ROM (@ IROM=1).
IROM
r/w1:
r/w0:
Internal ROM
Enable internal CPU ROM.
Disable internal CPU ROM.
IRAM
r/w1:
r/w0:
Internal RAM
Enable internal CPU RAM.
Disable internal CPU RAM.
ICPU
r/w1:
r/w0:
Internal CPU
Enable internal CPU.
Disable internal CPU.
88
Micronas