VCT 38xxA
ADVANCE INFORMATION
CPU RAM/ROM
Text RAM
TPU Address Space
≥128k Text RAM
19k Text RAM
16k Text RAM
000000H
0F8000H
0A8000H
0A0000H
088000H
080000H
078000H
000000H
000000H
000000H
Page
Table
000FFFH
Page
Table
Page
Table
reserved
001000H
Scratch
002000H
001000H
Scratch
001800H
001000H
Scratch
001800H
001E00H
002000H
DMA
TTX
Page
Page
Bank
Memory
Memory
084000H
087FFFH
003000H
003000H
008000H
OSD&TTX
Bank
OSD
Bank
16kbyte
004000H
004000H
OSD&TTX
Bank
Page
Memory
128kbyte
256kbyte
512kbyte
020000H
040000H
07FFFFH
00FFFFH
int. ROM
ext. ROM
int. RAM
ext. RAM
I/O-Reg
Fig. 5–6: Memory Banking shown with the maximal size of addressable memory
5.9. DMA Interface
The DMA interface connects the TPU SRAM interface
to the CPU memory bus (see Fig. 5–7). This is done to
avoid extra pins for external TPU page memory.
As long as the DMA interface is disabled, the TPU can-
not access the CPU address bus and therefore should
not transfer data to/from the internal/external SRAM.
To ensure this, the controller should reset the TPU
before disabling the DMA interface. After reset the
TPU will not access the memory until receiving the I2C
command “DRAM_MODE” (see Section 3.12. on
page 68).
The DMA interface must not be operated during CPU
Slow mode. The DMA interface can be disabled via
DMAIM.DMAEN.
96
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