欢迎访问ic37.com |
会员登录 免费注册
发布采购

VCT3801A 参数 Datasheet PDF下载

VCT3801A图片预览
型号: VCT3801A
PDF下载: 下载PDF文件 查看货源
内容描述: 视频/控制/图文电视IC系列 [Video/Controller/Teletext IC Family]
分类和应用: 电视
文件页数/大小: 172 页 / 2219 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号VCT3801A的Datasheet PDF文件第43页浏览型号VCT3801A的Datasheet PDF文件第44页浏览型号VCT3801A的Datasheet PDF文件第45页浏览型号VCT3801A的Datasheet PDF文件第46页浏览型号VCT3801A的Datasheet PDF文件第48页浏览型号VCT3801A的Datasheet PDF文件第49页浏览型号VCT3801A的Datasheet PDF文件第50页浏览型号VCT3801A的Datasheet PDF文件第51页  
ADVANCE INFORMATION  
VCT 38xxA  
3. Text and OSD Processing  
3.1. Introduction  
3.3. Text Controller  
The VCT 38xxA includes a World System Teletext  
(WST) decoder, whose display capabilities are also  
used for OSD generation. In the following sections the  
text and OSD processing part of the VCT 38xxA will be  
named TPU for short.  
The TPU operates with its own 65C02 core running at  
10.125 MHz. The core can address up to 64 kBytes of  
memory.  
The CPU memory contains 640 Bytes RAM, 12 kBytes  
program ROM and 12 kBytes character ROM. The  
character ROM holds the font data and is separated  
from the program ROM to save CPU time. The CPU  
can still access the character ROM via a DMA inter-  
face including wait cycles. The display controller can  
also access the CPU memory via the same DMA inter-  
face. By this means it is possible to locate part of the  
character font in program ROM or part of the program  
code in character ROM.  
With integrated CPU, RAM and ROM, an adaptive data  
slicer, a display controller, and a number of interfaces,  
the TPU offers acquisition and display of various tele-  
text and data services such as WST, PDC, VPS, and  
WSS. Fig. 3–1 shows the functional block diagram of  
the TPU.  
The TPU operates independently from the TV control-  
ler and can be controlled by software via I2C bus inter-  
face (see Section 3.14. on page 82). The TV controller  
is not burdened with the task of teletext decoding and  
communicates with the TPU via a high-level command  
language.  
Table 3–1: Memory map of text controller  
Interrupt Vector  
Absolute Address  
(High Byte, Low Byte)  
The TPU performs the following tasks:  
IRQ  
FFFF, FFFE  
FFFD, FFFC  
FFFB, FFFA  
FFF9  
– teletext data acquisition  
– teletext data decoding  
– page generation  
(hardware)  
(software)  
(software)  
(software)  
(hardware)  
(software)  
Reset  
NMI  
– page memory management  
– page display  
Control Word  
Memory Segment  
Zero Page  
Stack Page  
OSD Buffer  
I/O Page  
Absolute Address  
0000 00FF  
0100 01FF  
0100 019F  
0200 02FF  
0300 037F  
5000 7FFF  
D000 FFFF  
– user interface  
3.2. SRAM Interface  
The SRAM interface connects a standard SRAM to the  
internal bus structure. The address bus is 19 bit wide,  
addressing SRAMs up to 4 Mbit. Smaller SRAMs can  
also be connected.  
Extra Page  
Character ROM  
Program ROM  
The SRAM interface has to handle 3 asynchronous  
data streams. The CPU needs access to every mem-  
ory location of the SRAM. During VBI the slicer writes  
up to 22 teletext lines of 43 Bytes into the acquisition  
scratch memory. During text display the display con-  
troller copies teletext rows from display memory into its  
internal row buffer.  
On VCT 38xxA the SRAM interface of the TPU is con-  
nected to the memory bus of the TV controller. This is  
done to save pins and to give the TV controller faster  
access to the display memory. Refer to DMA Interface  
(chapter 5.9. on page 96) for more details.  
After reset the TPU will not use the SRAM interface  
until receiving the I2C command “DRAM_MODE” (see  
Section 3.12. on page 68).  
Micronas  
47  
 复制成功!