TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
2
2
4.2. I C Bus Interface
The time required to process the I C buffer depends on
other processes running inside the TPU 3040 firmware.
2
Thus the following I C telegram addressing the TPU can
Communication between TPU 3040 and host controller
be held after the slave address byte until the old tele-
gram is completely processed.
2
2
is done via I C-bus. For detailed information on the I C-
2
bus please refer to the Philips manual ‘I C-bus Specifi-
cation’.
4.2.1. Subaddressing
The TPU 3040 acts as a slave transmitter/receiver and
uses clock synchronization to slow down the data trans-
fer if necessary. General call address will not be ac-
knowledged.
Access to all memory locations and to the command in-
terface is achieved by subaddressing. Both the external
DRAM and the internal CPU memory can be addressed
completely. The TPU 3040 acknowledges 6 different
subaddresses following the slave address (see Table
4–2).
Different memories and functions of TPU 3040 can be
accessed by subaddressing. The byte following the
slave address byte is defined as the subaddress byte.
2
The following symbols are used to describe the I C ex-
ample telegrams:
2
Maximum length of an I C telegram is 256 bytes follow-
ing slave address and subaddress byte. The interface
supports data transfer with autoincrement.
<
>
start condition
stop condition
address bank byte
address high byte
address low byte
command byte
data byte
status byte
0 – n continuation bytes
2
The I C-bus interface is interrupt-driven and uses an in-
ab
ah
al
cc
dd
ss
..
2
ternal 48-byte buffer to collect I C data in real-time with-
out disturbing internal processes. This is done to avoid
clock synchronization as far as possible. When the TPU
2
2
3040 has to process the I C buffer and the I C telegram
2
has not yet been stopped, the I C clock line will be held
down.
2
Table 4–2: I C-bus Subaddresses
Name
TPU
Binary Value
0010 001x
0111 1000
0111 1001
0111 1010
0111 1011
0111 1100
0111 1101
Hex Value
Mode
W, R
W
Function
22, 23
78
TPU slave address
Sub 1
Sub 2
Sub 3
Sub 4
Data
subaddressing CPU (static)
79
W
subaddressing CPU (autoincrement)
subaddressing DRAM (autoincrement)
subaddressing command language
subaddressing data register
7A
W
7B
W
7C
R/W
R
Status
7D
status register
bit 7 = command wait
bit 6 = command invalid
bit 5 = command found no data
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = 0
bit 0 = 0
24
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
