SDA9410
Preliminary Data Sheet
Operating range
Parameter
Symbol Min
Nom Max Unit Remark
Input SYNCENS
Low time
tWL
22
22
ns
see "Timing
diagram clock" on
page 177
High time
tWH
tTLH
tTHL
ns
ns
ns
Rise time
10
10
Fall time
Clock TTL Input X1/CLKD
Clock frequency
27
MHz see "Timing
diagram clock" on
1/T
page 177
Low time
High time
Rise time
Fall time
tWL
10
10
ns
ns
ns
ns
tWH
tTLH
tTHL
5
5
I²C Bus (All Values Are Referred To min(VIH) And max(VIL)), fSCL = 400 KHz
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
3
5.25
1.5
V
V
see "I²C Bus timing
START/STOP" on
page 176
0
see "I²C Bus timing
DATA" on
page 176
SCL Clock Frequency
Inactive Time Before Start Of Transmission
Set-Up Time Start Condition
Hold Time Start Condition
SCL Low Time
fSCL
0
400 kHz
tBUF
1.3
0.6
0.6
1.3
0.6
100
0
µs
tSU;STA
tHD;STA
tLOW
tHIGH
tSU;DAT
tHD;DAT
tR
µs
µs
µs
SCL High Time
µs
Set-Up Time DATA
ns
Hold Time DATA
µs
SDA/SCL Rise Times
SDA/SCL Fall Times
300 ns
300 ns
µs
tF
Set-Up Time Stop Condition
Output valid from clock
tSU;STO
tAA
0.6
900 ns
Input filter spike suppression (SDA and SCL
pins)
tSP
50
ns
Low-Level Output Current
IOL
3
mA
172
Micronas
MICRONAS [ MICRONAS ]
