Source Select
SCART DSP Input Select
SCART Output Select
8
ANA_IN1+
ANA_IN2+
AGC
A
D
DEMODULATOR
(incl. Carrier Mute)
Deemphasis:
50/75
µs
DBX/MNR
Panda1
FM/AM
Prescale
(0E
hex
)
Fig. 2–1 shows a simplified block diagram of the IC.
The block diagram contains all features of the
2.1. Architecture of the MSP 44x8G Family
2. Functional Description
MSP 44x8G
Automatic
Soundselect
FM/AM
Stereo or A
Stereo or A
Stereo or B
0
1
3
4
Main
Channel
Matrix
(08
hex
)
AVC*
Σ
Volume
D
A
DACM_L
DACM_R
Decoded
Standards:
NICAM
A2
AM
BTSC
EIA-J
SAT
FM-Radio
ADR-Bus
Interface
(29
hex
)
(00
hex
)
Deemphasis:
J17
NICAM
Beeper
(14
hex
)
Prescale
(10
hex
)
Aux
Channel
Matrix
(09
hex
)
Volume
Σ
D
A
DACA_L
Standard
and Sound
Detection
I
2
C
Read
Register
I
2
S
Channel
Matrix
Preem-
phasis
(34
hex
)
(06
hex
)
DACA_R
I
2
S
Interface
(0B
hex
)
I2S_DA_OUT
(sync. 48 kHz)
I2S_DA_IN1
(sync. 48 kHz)
I2S_CL
I2S_WS
I S
Interface
2
I
2
S1
5
Prescale
I
2
S2
(16
hex
)
Quasi-Peak
Channel
Matrix
(0C
hex
)
Quasi-Peak
Detector
I
2
C
Read
Register
I2S_DA_IN2
(sync. 48 kHz)
I
2
S
Interface
6
Prescale
I
2
S3
7
Prescale
(11
hex
)
(12
hex
)
Note:
*
AVC
location is
programmable
I2S_CL3
I2S_WS3
I2S_DA_IN3
(async. 5-50 kHz)
I
2
S
Interface
Synchronization /
Interpolation
Mix1
Channel
Matrix
Mix2
Channel
Matrix
Mix1
scale
Mix2
scale
(3B )
hex
(38
hex
)
(3A
hex
)
Σ
AVC*
MSP 4458G. Other members of the MSP 44x8G family
do not have the complete set of features, handling only
a subset of the standards (see dashed block in
Fig. 2–1).
15
(39
hex
)
(29
hex
)
A
D
SCART
2
Prescale
(0D
hex
)
SCART1
Channel
Matrix
(0A
hex
)
Volume
D
A
SCART1_L/R
SC1_OUT_L
(07
hex
)
SCART2
Channel
Matrix
(41
hex
)
Volume
D
A
SCART2_L/R
SC1_OUT_R
PRELIMINARY DATA SHEET
(13
hex
)
(40
hex
)
SC1_IN_L
SC1_IN_R
SC2_IN_L
SC2_IN_R
SC3_IN_L
SC3_IN_R
SC4_IN_L
SC4_IN_R
MONO_IN
SC2_OUT_L
SC2_OUT_R
Micronas
(13
hex
)
Fig. 2–1:
Signal flow block diagram of the MSP 44x8G (input and output names correspond to pin names).
MICRONAS [ MICRONAS ]
