MSP 44x8G
PRELIMINARY DATA SHEET
I2S_CL3
1/F
I2S3WS
2
2
Left sample (I S_CONFIG[10] = 0)
Right sample (I S_CONFIG[10] = 0)
I2S_WS3
2
2
Right sample (I S_CONFIG[10] = 1)
Left sample (I S_CONFIG[10] = 1)
2
Left aligned (I S_CONFIG[9] = 0)
I2S_DA_IN3
I2S_DA_IN3
16,18...32 Bit data & clocks allowed
MSB
MSB
2
Left aligned (I S_CONFIG[9] = 1)
16,18...32 Bit data & clocks allowed
MSB
MSB
2
2
I2S_DA_IN3
Right aligned (I S_CONFIG[11] = 1, I S_CONFIG[9] = 0)
16 Bit data & 16...32 clocks allowed
LSB
LSB
1/F
I2S3CL
I2S_CL3
T
T
s_I2S3
h_I2S3
I2S_DA_IN3
I2S_WS3
T
s_I2S3
Fig. 4–23: I2S timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Ground
V
AGNDC Open Circuit Voltage
8-V Operation:
AGNDC
R
≥10 MΩ
load
AGNDC0
3.77
2.49
V
V
5-V Operation:
R
AGNDC Output Resistance
8-V Operation:
3 V ≤ V
≤ 4 V
outAGN
AGNDC
70
47
125
83
180
120
kΩ
kΩ
5-V Operation:
Analog Input Resistance
1)
R
SCART Input Resistance
SCn_IN_s
25
15
40
24
58
35
kΩ
kΩ
f
f
= 1 kHz, I = 0.05 mA
= 1 kHz, I = 0.1 mA
inSC
signal
from T = 0 to 70 °C
A
R
MONO Input Resistance
MONO_IN
inMONO
signal
from T = 0 to 70 °C
A
1)
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”
60
Micronas
MICRONAS [ MICRONAS ]
