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MSP34X2G 参数 Datasheet PDF下载

MSP34X2G图片预览
型号: MSP34X2G
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频处理器系列与杜比定向逻辑 [Multistandard Sound Processor Family with Dolby Surround Pro Logic]
分类和应用:
文件页数/大小: 104 页 / 1165 K
品牌: MICRONAS [ MICRONAS ]
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MSP 34x2G  
PRELIMINARY DATA SHEET  
6.5.6. Identification Mode for A2 Stereo Systems  
6.6. Manual/Compatibility Mode:  
Description of DSP Read Registers  
Identification Mode  
00 15hex  
L
All readable registers are 16-bit wide. Transmissions  
via I2C bus have to take place in 16-bit words. Some of  
the defined 16-bit words are divided into low and high  
byte, thus holding two different control entities.  
Standard B/G  
(German Stereo)  
0000 0000  
RESET  
00hex  
Standard M  
(Korean Stereo)  
0000 0001  
0011 1111  
01hex  
3Fhex  
These registers are not writable.  
Reset of Ident-Filter  
6.6.1. Stereo Detection Register  
for A2 Stereo Systems  
To shorten the response time of the identification algo-  
rithm after a program change between two FM-Stereo  
capable programs, the reset of the ident-filter can be  
applied.  
Stereo Detection  
Register  
00 18hex  
H
Stereo Mode  
Reading  
(two’s complement)  
Sequence:  
1. Program change  
MONO  
near zero  
2. Reset ident-filter  
STEREO  
positive value (ideal  
reception: 7Fhex  
)
3. Set identification mode back to standard B/G or M  
4. Wait approx. 500 ms  
BILINGUAL  
negative value (ideal  
reception: 80hex)  
5. Read stereo detection register  
Note: This register is initialized during STANDARD  
SELECTION and is automatically updated when Auto-  
matic Sound Select (MODUS[0]=1) is on.  
Note: It is no longer necessary to read out and evalu-  
ate the A2 identification level. All evaluation is per-  
formed in the MSP and indicated in the STATUS regis-  
ter.  
6.5.7. FM DC Notch  
6.6.2. DC Level Register  
The DC compensation filter (FM DC Notch) for FM  
input can be switched off. This is used to speed up the  
automatic search function (see Section 6.4.7.). In nor-  
mal FM-mode, the FM DC Notch should be switched  
on.  
DC Level Readout  
FM1 (MSP-Ch2)  
00 1Bhex  
00 1Chex  
H+L  
H+L  
DC Level Readout  
FM2 (MSP-Ch1)  
FM DC Notch  
00 17hex  
L
DC Level  
[8000hex ... 7FFFhex]  
values are 16 bit two’s  
complement  
ON  
0000 0000  
Reset  
00hex  
OFF  
0011 1111  
3Fhex  
The DC level register measures the DC component of  
the incoming FM signals (FM1 and FM2). This can be  
used for seek functions in satellite receivers and for IF  
FM frequencies fine tuning. A too low demodulation  
frequency (DCO) results in a positive DC-level and  
vice versa. For further processing, the DC content of  
the demodulated FM signals is suppressed. The time  
constant τ, defining the transition time of the DC Level  
Register, is approximately 28 ms.  
98  
Micronas