欢迎访问ic37.com |
会员登录 免费注册
发布采购

MSP34X2G 参数 Datasheet PDF下载

MSP34X2G图片预览
型号: MSP34X2G
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频处理器系列与杜比定向逻辑 [Multistandard Sound Processor Family with Dolby Surround Pro Logic]
分类和应用:
文件页数/大小: 104 页 / 1165 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号MSP34X2G的Datasheet PDF文件第82页浏览型号MSP34X2G的Datasheet PDF文件第83页浏览型号MSP34X2G的Datasheet PDF文件第84页浏览型号MSP34X2G的Datasheet PDF文件第85页浏览型号MSP34X2G的Datasheet PDF文件第87页浏览型号MSP34X2G的Datasheet PDF文件第88页浏览型号MSP34X2G的Datasheet PDF文件第89页浏览型号MSP34X2G的Datasheet PDF文件第90页  
MSP 34x2G  
PRELIMINARY DATA SHEET  
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode  
Table 6–1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!  
Demodulator  
Write Registers  
Address MSP-  
Description  
Reset  
Mode  
Page  
(hex)  
Version  
AUTO_FM/AM  
00 21  
3411,  
3451  
1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of 00 00  
Automatic Switching between NICAM and FM/AM in case of bad NICAM  
reception  
87  
1)  
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic  
Switching between NICAM and FM/AM in case of bad NICAM reception  
A2_Threshold  
CM_Threshold  
AD_CV  
00 22  
00 24  
00 BB  
00 83  
all  
A2 Stereo Identification Threshold  
00 19  
89  
89  
90  
91  
hex  
all  
Carrier-Mute Threshold  
00 2A  
00 00  
hex  
all  
SIF-input selection, configuration of AGC, and Carrier-Mute Function  
MODE_REG  
3411,  
3451  
Controlling of MSP-Demodulator and Interface options. As soon as this 00 00  
register is applied, the MSP 34x2G works in the MSP 34x0D Compatibility  
Mode.  
1)  
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only  
MSP 34x0D features are available; the use of MODUS and STATUS register  
is not allowed.  
The MSP 34x2G is reset to the normal mode by first programming the  
MODUS register followed by transmitting a valid standard code to the  
STANDARD SELECTION register.  
FIR1  
FIR2  
00 01  
00 05  
FIR1-filter coefficients channel 1 (6 8 bit)  
FIR2-filter coefficients channel 2 (6 8 bit), + 3 8 bit offset (total 72 bit)  
00 00  
00 00  
93  
93  
DCO1_LO  
DCO1_HI  
00 93  
00 9B  
Increment channel 1 Low Part  
Increment channel 1 High Part  
DCO2_LO  
DCO2_HI  
00 A3  
00 AB  
Increment channel 2 Low Part  
Increment channel 2 High Part  
PLL_CAPS  
00 1F  
Not of interest for the customer  
00 56  
96  
Switchable PLL capacitors to tune open-loop frequency  
1)  
not in BTSC, EIA-J, and FM-Radio mode  
Note: All registers except AUTO_FM/AM, A2_Threshold and CM-Threshold are initialised during STANDARD SELECTION and are  
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.  
Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!  
Demodulator  
Address MSP-  
Description  
Page  
Read Registers  
(hex)  
00 23  
00 38  
00 3E  
00 57  
02 1F  
02 1E  
Version  
C_AD_BITS  
ADD_BITS  
CIB_BITS  
3411,  
3451  
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits  
NICAM: bit [10:3] of additional data bits  
NICAM: CIB1 and CIB2 control bits  
NICAM error rate, updated with 182 ms  
Not for customer use  
95  
95  
95  
96  
96  
96  
ERROR_RATE  
PLL_CAPS  
AGC_GAIN  
Not for customer use  
86  
Micronas  
 复制成功!