PRELIMINARY DATA SHEET
MSP 34x2G
1/F
I2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Detail B
I2S_DA_OUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Data: MSB first, I2S master
1/F
I2SWS
I2S_WS
MODUS[6] = 0
MODUS[6] = 1
Detail C
I2S_CL
Detail A
I2S_DA_IN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16,18...32 bit left channel
16, 18...32 bit left channel
16, 18...32 bit right channel
Detail B
I2S_DA_OUT R LSB
L MSB
L LSB R MSB
R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S slave
Detail C
Detail A,B
1/F
I2SCL
I2S_CL
I2S_CL
T
T
h_I2S
s_I2S
T
s_I2S
I2S_DA_IN1/2
I2S_WS as INPUT
T
d_I2S
T
d_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4–22: I2S bus timing diagram
Micronas
71
MICRONAS [ MICRONAS ]
