MSP 34x1G
PRELIMINARY DATA SHEET
(Data: MSB first)
F
I2SWS
I2S_WS
SONY Mode
SONY Mode
PHILIPS Mode
PHILIPS Mode
PHILIPS/SONY Mode programmable by MODUS[6]
Detail C
I2S_CL
Detail A
Detail B
I2S_DAIN
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
16 bit left channel
16 bit right channel
I2S_DAOUT
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit right channel
Detail C
Detail A,B
F
I2SCL
I2S_CL
I2S_CL
T
T
T
I2S2
I2S1
T
T
T
I2SWS1
I2SWS2
I2S_WS as INPUT
I2S_DA_IN
T
T
I2S3
I2S4
I2S5
I2S6
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4–26: I2S bus timing diagram
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Ground
V
AGNDC Open Circuit Voltage
(8-V Operation)
AGNDC
3.67
2.41
70
3.77
2.51
125
83
3.87
2.61
180
120
V
R
≥10 MΩ
load
AGNDC0
AGNDC Open Circuit Voltage
(5-V Operation)
V
R
AGNDC Output Resistance
(8-V Operation)
kΩ
kΩ
3 V ≤ V
≤ 4 V
outAGN
AGNDC
AGNDC Output Resistance
(5-V Operation)
47
Analog Input Resistance
1)
R
SCART Input Resistance
SCn_IN_s
25
15
40
24
58
35
kΩ
kΩ
f
f
= 1 kHz, I = 0.05 mA
= 1 kHz, I = 0.1 mA
inSC
signal
from T = 0 to 70 °C
A
R
MONO Input Resistance
MONO_IN
inMONO
signal
from T = 0 to 70 °C
A
1)
“n” means “1”, “2”, “3”, or “4”;
“s” means “L” or “R”
70
MICRONAS INTERMETALL
MICRONAS [ MICRONAS ]
