PRELIMINARY DATA SHEET
MSP 34x7G
2.6. SCART Signal Routing
2.7. Digital Control I/O Pins and
Status Change Indication
2.6.1. SCART DSP In and SCART Out Select
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 28). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The SCART DSP Input Select and SCART Output
Select blocks include switching facilities. The switches
are controlled by the ACB user register (see page 28).
2.6.2. Stand-by Mode
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 21).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 22).
If the MSP 34x7G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(‘Stand-by’-mode), the SCART switches maintain
their position and function. This allows the copying
from SCART-input to SCART-output in the TV set’s
stand-by mode.
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary; I2C-bus interactions are reduced to a
minimum (see STATUS register on page 22 and
MODUS register on page 21).
In case of power on or starting from stand-by (switch-
ing on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB regis-
ter (page 28) are reset to the default configuration (see
Table 3–5 on page 17). The reset position of the ACB
register becomes active after the first I2C transmission
into the Baseband Processing part. By transmitting the
ACB register first, the reset state can be redefined.
2.8. Clock PLL Oscillator and
Crystal Specifications
The MSP 34x7G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM mode, the
clock is phase-locked to the corresponding source.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note, that for the
phase-locked mode (NICAM), crystals with tighter tol-
erance are required.
Micronas
13
MICRONAS [ MICRONAS ]
