MSP 34x0G
DATA SHEET
2.6.2. Stand-by Mode
2.8. ADR Bus Interface
If the MSP 34x0G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(‘Stand-by’-mode), the SCART switches maintain
their position and function. This allows the copying
from SCART-input to SCART-output in the TV set’s
stand-by mode.
For the ASTRA Digital Radio System (ADR), the
MSP 3400G, MSP 3410G, and MSP 3450G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x0G should be provided on a
feature connector:
In case of power on or starting from stand-by (switch-
ing on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB regis-
ter (see page 41) are reset to the default configuration
(see Table 3–5 on page 20). The reset position of the
ACB register becomes active after the first I2C trans-
mission into the Baseband Processing part. By trans-
mitting the ACB register first, the reset state can be
redefined.
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
– I2S_WS
– I2S_CL
– ADR_CL, ADR_WS, ADR_DA
2.7. I2S Bus Interface
For more details, please refer to the DRP 3510A data
sheet.
The MSP 34x0G has a synchronous master/slave
input/output interface running on 32 kHz.
2.9. Digital Control I/O Pins and
Status Change Indication
The interface accepts two formats:
1. I2S_WS changes at the word boundary
2. I2S_WS changes one I2S-clock period before the
word boundaries.
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 41). This enables the controlling of external
hardware switches or other devices via I2C-bus.
All I2S options are set by means of the MODUS and
the I2S_CONFIGURATION registers.
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 26).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 28).
The I2S bus interface consists of five pins:
– I 2 S _ D A _ I N 1 , I 2 S _ D A _ I N 2 :
I2S serial data input: 16, 18....32 bits per sample
– I2S_DA_OUT:
I2S serial data output: 16, 18...32 bits per sample
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I2C bus interactions are reduced to a
minimum (see STATUS register on page 28 and
MODUS register on page 26).
– I2S_CL:
I2S serial clock
– I2S_WS:
I2S word strobe signal defines the left and right
sample
If the MSP 34x0G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the IC. In this mode, only 16 or 32 bits per sample can
be selected. In slave mode, these lines are input to the
IC and the MSP clock is synchronized to 576 times the
I2S_WS rate (32 kHz). NICAM operation is not possi-
ble in slave mode.
2.10. Clock PLL Oscillator and Crystal Specifications
The MSP 34x0G derives all internal system clocks
from the 18.432 MHz oscillator. In NICAM or in I2S-
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I2S-Slave mode at the same time.
An I2S timing diagram is shown in Fig. 4–27 on
page 73.
For proper performance, the MSP clock oscillator
requires a 18.432 MHz crystal. Note that for the
phase-locked modes (NICAM, I2S-Slave), crystals with
tighter tolerance are required.
16
May 27, 2003; 6251-476-1DS
Micronas
MICRONAS [ MICRONAS ]
