DATA SHEET
MSP 34x0G
4.4. Pin Configurations
AUD_CL_OUT
NC
1
2
3
4
5
6
7
8
9
64 TP
TP
AUD_CL_OUT
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
1
2
3
4
5
6
7
8
9
52 XTAL_OUT
51 XTAL_IN
50 TESTEN
49 ANA_IN2+
48 ANA_IN−
47 ANA_IN1+
46 AVSUP
63 XTAL_OUT
62 XTAL_IN
61 TESTEN
60 ANA_IN2+
59 ANA_IN−
58 ANA_IN+
57 AVSUP
NC
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
STANDBYQ
NC
STANDBYQ
I2C_CL
I2C_DA
45 AVSS
I2C_CL
56 AVSS
I2S_CL
44 MONO_IN
43 VREFTOP
42 SC1_IN_R
41 SC1_IN_L
40 SC2_IN_R
39 SC2_IN_L
38 SC3_IN_R
37 SC3_IN_L
36 AGNDC
I2C_DA 10
I2S_CL 11
I2S_WS 12
I2S_DA_OUT 13
I2S_DA_IN1 14
ADR_DA 15
ADR_WS 16
ADR_CL 17
DVSUP 18
DVSS 19
55 MONO_IN
54 VREFTOP
53 SC1_IN_R
52 SC1_IN_L
51 ASG
I2S_WS 10
I2S_DA_OUT 11
I2S_DA_IN1 12
ADR_DA 13
ADR_WS 14
ADR_CL 15
DVSUP 16
50 SC2_IN_R
49 SC2_IN_L
48 ASG
DVSS 17
47 SC3_IN_R
46 SC3_IN_L
45 ASG
I2S_DA_IN2 18
NC 19
35 AHVSS
34 CAPL_M
33 AHVSUP
32 CAPL_A
31 SC1_OUT_L
30 SC1_OUT_R
29 VREF1
I2S_DA_IN2 20
NC 21
RESETQ 20
DACA_R 21
DACA_L 22
VREF2 23
44 SC4_IN_R
43 SC4_IN_L
42 AGNDC
41 AHVSS
NC 22
NC 23
RESETQ 24
DACA_R 25
DACA_L 26
VREF2 27
DACM_R 28
DACM_L 29
NC 30
DACM_R 24
DACM_L 25
DACM_SUB 26
40 CAPL_M
39 AHVSUP
38 CAPL_A
37 SC1_OUT_L
36 SC1_OUT_R
35 VREF1
28 SC2_OUT_L
27 SC2_OUT_R
Fig. 4–7: PSDIP52-1/-2 package
DACM_SUB 31
NC 32
34 SC2_OUT_L
33 SC2_OUT_R
Fig. 4–6: PSDIP64-1 package
Micronas
May 27, 2003; 6251-476-1DS
57
MICRONAS [ MICRONAS ]
