欢迎访问ic37.com |
会员登录 免费注册
发布采购

MSP3440G 参数 Datasheet PDF下载

MSP3440G图片预览
型号: MSP3440G
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频处理器系列 [Multistandard Sound Processor Family]
分类和应用:
文件页数/大小: 106 页 / 1906 K
品牌: MICRONAS [ MICRONAS ]
 浏览型号MSP3440G的Datasheet PDF文件第24页浏览型号MSP3440G的Datasheet PDF文件第25页浏览型号MSP3440G的Datasheet PDF文件第26页浏览型号MSP3440G的Datasheet PDF文件第27页浏览型号MSP3440G的Datasheet PDF文件第29页浏览型号MSP3440G的Datasheet PDF文件第30页浏览型号MSP3440G的Datasheet PDF文件第31页浏览型号MSP3440G的Datasheet PDF文件第32页  
MSP 34x0G  
DATA SHEET  
3.3.2.5. Read Registers on I2C Subaddress 11hex  
Table 3–10: Read Registers on I2C Subaddress 11hex  
Register  
Address  
Function  
Name  
00 7Ehex  
STANDARD RESULT Register  
STANDARD_RES  
Readback of the detected TV sound or FM-Radio Standard  
bit[15:0] 00 00hex Automatic Standard Detection could not find  
a sound standard  
00 02hex MSP Standard Codes (see Table 3–8 on page 25)  
...  
00 40hex  
>07 FFhex Automatic Standard Detection still active  
02 00hex  
STATUS Register  
STATUS  
Contains all user relevant internal information about the status of the MSP  
bit[15:10]  
bit[8]  
undefined  
0/1  
“1” indicates bilingual sound mode or SAP present  
(internally evaluated from received analog or digital  
identification signals)  
bit[7]  
bit[6]  
0/1  
0/1  
“1” indicates independent mono sound (only for  
NICAM)  
mono/stereo indication  
(internally evaluated from received analog or digital  
identification signals)  
bit[5,9]  
00  
01  
10  
11  
analog sound standard (FM or AM) active  
this pattern will not occur  
digital sound (NICAM) available  
bad reception condition of digital sound (NICAM) due  
to:  
a. high error rate  
b. unimplemented sound code  
c. data transmission only  
bit[4]  
bit[3]  
bit[2]  
0/1  
0/1  
low/high level of digital I/O pin D_CTR_I/O_1  
low/high level of digital I/O pin D_CTR_I/O_0  
0
1
detected secondary carrier (2nd A2 or SAP sub-carrier)  
no secondary carrier detected  
bit[1]  
bit[0]  
0
1
detected primary carrier (Mono or MPX carrier)  
no primary carrier detected  
undefined  
If STATUS change indication is activated by means of MODUS[1]: Each  
change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high  
level. Reading the STATUS register resets D_CTR_I/O_1.  
28  
May 27, 2003; 6251-476-1DS  
Micronas