DATA SHEET
MSP 34x0G
1
0
I2C_DA
I2C_CL
S
P
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.4. Proposals for General MSP 34x0G
I2C Telegrams
3.2. Start-Up Sequence:
Power-Up and I2C-Controlling
3.1.4.1. Symbols
After POWER-ON or RESET (see Fig. 4–24), the IC is
in an inactive state. All registers are in the Reset posi-
tion (see Table 3–5 and Table 3–6), the analog out-
puts are muted. The controller has to initialize all regis-
ters for which a non-default setting is necessary.
daw
dar
<
write device address (80hex, 84hex or 88hex)
read device address (81hex, 85hex or 89hex
Start Condition
)
>
Stop Condition
aa
dd
Address Byte
Data Byte
3.3. MSP 34x0G Programming Interface
3.3.1. User Registers Overview
3.1.4.2. Write Telegrams
The MSP 34x0G is controlled by means of user regis-
ters. The complete list of all user registers are given in
Table 3–5 and Table 3–6. The registers are partitioned
into the Demodulator section (Subaddress 10hex for
writing, 11hex for reading) and the Baseband Process-
ing sections (Subaddress 12hex for writing, 13hex for
reading).
<daw 00 d0 00>
write to CONTROL register
write data into demodulator
write data into DSP
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
3.1.4.3. Read Telegrams
<daw 00 <dar dd dd>
read data from
CONTROL register
Write and read registers are 16 bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I2C bus
have to take place in 16-bit words (two byte transfers, with
the most significant byte transferred first). All write regis-
ters, except the demodulator write registers are readable.
<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP
3.1.4.4. Examples
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
<80 00 80 00>
RESET MSP statically
Clear RESET
<80 00 00 00>
<80 10 00 30 00 01>
<80 10 00 20 00 03>
Automatic Sound Select = ON
Set demodulator to stand. 03hex
For reasons of software compatibility to the
MSP 34xxD, a Manual/Compatibility Mode is available.
More read and write registers together with a detailed
description can be found in “Appendix B: Manual/Com-
patibility Mode” on page 87.
<80 11 02 00 <81 dd dd> Read STATUS
<80 12 00 08 01 20> Set loudspeaker channel
source to Stereo or A/B and
Matrix to Stereo
(transparent mode)
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 43.
Micronas
May 27, 2003; 6251-476-1DS
19
MICRONAS [ MICRONAS ]
