MSP 3400C
PRELIMINARY DATA SHEET
7.3. Summary of Readable Registers
All readable registers are 16 bit wide. Transmissions via
2
I C bus have to take place in 16 bit words. Single data
entries are 8 bit. Some of the defined 16 bit words are
divided into low and high byte, thus holding two different
control entities.
These registers are not writeable.
Name
Address
High/Low
Output Range
Stereo detection register
Quasi peak readout left
Quasi peak readout right
DC level readout FM1/Ch2–L
DC level readout FM2/Ch1–R
MSP hardware version code
MSP major revision code
0018
0019
001a
001b
001c
001e
H
[80
[00
[00
[00
[00
[00
[00
[00
[00
... 7F
hex
]
8 bit two’s complement
16 bit binary
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
H&L
H&L
H&L
H&L
H
... 7FFF
... 7FFF
... 7FFF
... 7FFF
]
]
]
]
hex
hex
hex
hex
16 bit binary
16 bit binary
16 bit binary
... FF
... FF
... 0A
... FF
]
]
]
]
hex
hex
hex
hex
L
MSP product code
001f
H
hex
MSP ROM version code
L
7.3.1. Stereo Detection Register
7.3.2. Quasi Peak Detector
Stereo Detection
Register
0018
H
Quasi peak readout
left
0019
001a
H+L
H+L
hex
hex
Stereo Mode
Reading
(two’s complement)
Quasi peak readout
right
hex
MONO
near zero
Quasi peak readout
[0
... 7FFF
]
hex
hex
values are 16 bit binary
STEREO
positive value (ideal
reception: 7F
)
hex
The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to ad-
just all inputs to the same normalized listening level. The
refresh rate is 32 kHz. The feature is based on a filter
time constant:
BILINGUAL
negative value (ideal
reception: 80
hex)
attack-time: 1.3 ms
decay-time: 37 ms
MICRONAS INTERMETALL
41
MICRONAS [ MICRONAS ]
