DA9090B.001
January 14, 1998
PIN CONFIGURATION
SO28
TQFP44
NC
VCCA
VCCP
NC
SP1-
SP1+
SP2-
SP2+
GNDP
RX
1
2
3
4
5
6
7
8
9
10
28 MIC3+
27 MIC3-
26 GNDA
25 MIC1+
24 MIC1-
23 MIC2+
22 MIC2-
21 LO
20 MCLK
19 FS
18 GND
17 TX
16 CO
15 VCC
12 13 14 15 16 17 18 19 20 21 22
N N C C C B V C T G N
C C C S I Z C O X N C
D
L
C
K
1
NC
SP1- 2
3
SP1
NC
4
SP2- 5
SP2
6
NC
7
GNDP 8
9
NC
10
RX
11
NC
33
32
31
30
29
28
27
26
25
24
23
MIC1-
NC
MIC2+
MIC2-
NC
NC
NC
LO
MCLK
FS
NC
V
C
N N C
C C P
V
C
C N N
A C C
M
I
C
3
+
M
I
C
3
-
M
G
I
N
C
D N 1
A C +
44 43 42 41 40 39 38 37 36 35 34
CCLK 11
CS
CI
BZ
12
13
14
PIN DESCRIPTION
Pin Name
Pin Number
SO28
TQFP44
1,4
1,4,7,9
11,12,13
22,23,27
28,29,32
35,39,40,
43,44
41
42
2
3
5
6
8
10
14
15
16
17
18
19
20
Type
Function
No connection.
VCCA
VCCP
SP1-
SP1+
SP2-
SP2+
GNDP
RX
CCLK
CS
CI
BZ
VCC
CO
TX
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
P
P
AO
AO
AO
AO
G
DI
DI
DI
DI
AO
P
DO
DO
GND
FS
18
19
21
24
G
DI
Positive power supply input for analog section.
Positive power supply input for speaker amplifiers.
Speaker 1 amplifier negative output.
Speaker 1 amplifier positive output.
Speaker 2 amplifier negative output.
Speaker 2 amplifier positive output.
Speaker amplifier.
Receive data input.
Control clock input. Shifts serially into CI and CO when CS is
low. CCLK is asynchronous with other system clocks.
Chip select input.
Control data input.
Buzzer driver output.
Positive power supply input for the digital section. VCCA,
VCCP AND VCC must be connected together.
Control data output.
Transmit data output. Data is shifted out on this during the
assigned transmit slots. Otherwise, TX is on high impedance
state.
Ground for the digital section.
Frame sync input. This 8kHz signal defines the start of the TX
and RX frames.
2
MICRONAS [ MICRONAS ]
