DA9090B.001
January 14, 1998
TIMING SPECIFICATIONS
x
Serial Control Port Timing
Parameter
Frequency of CCLK
Period of CCLK high
Period of CCLK low
Rise time of CCLK
Fall time of CCLK
Hold time, CCLK high to CS low
Setup time, CS low to CCLK high
Setup time, valid CI data to CCLK high
Hold time, CCLK high to invalid CI data
Delay time, CCLK low to valid CO data
Delay time, CS low to valid CO data
Delay time, CS high or 8 CCLK low to
CO high impedance
th
Hold time, 8 CCLK high to CS high
Setup time, CS high to CCLK high
th
Symbol
f
CCLK
t
WHC
t
WLC
t
RC
t
FC
t
HCHS
t
SSLCH
t
SDCH
t
HCHD
t
DCLD
t
DSD
t
DSZ
t
H8CHS
t
SSHCH
Conditions
Min
Typ
Max
2.048
Unit
MHz
ns
ns
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
160
160
50
50
10
50
50
50
ns
ns
ns
ns
ns
ns
Load = 100 pF
10
100
100
80
50
80
ns
ns
ns
ns
ns
x
Serial Control Port Timing Diagram (MICROWIRE mode)
t
WHC
CCLK
1
2
3
4
5
t
WLC
6
7
8
t
HCHS
1
2
3
t
RC
4
t
FC
5
6
7
8
t
SSLCH
t
HCHS
CS
BYTE 1
t
SSHCH
BYTE 2
t
HCHSH
t
SDCH
t
HCHD
CI
7
6
5
4
3
2
1
0
t
HCHSH
t
SSLCH
7
6
5
4
3
2
1
0
t
DSD
CO
7
t
DCLD
6
5
4
3
2
1
t
DSZ
0
7
MICRONAS [ MICRONAS ]
