MAS 35x9F
DATA SHEET
MICIN
INL
INR
XVDD
A
−
+
SPDI1,
SPDI2
−
D
+
SPDIR
AGNDC
XVDD
Fig. 4–14: Analog input pins MICIN, INL, INR
Bias
Fig. 4–18: S/PDIF inputs
+
−
AGNDC
MICBI
VBAT
+
VREF
−
programmable
=
Fig. 4–15: Microphone bias pin (MICBI)
VSS
VSS
Fig. 4–19: Battery voltage monitor VBAT
FILTL(R)
4.5.1.Reset Pin Configuration for MAS 3529F and
MAS 3539F
D
I
−
+
A
OUTL(R)
The Power-On Reset pin POR is used to reset the
entire MAS 35x9F. The POR is an active-low signal.
AGNDC
Note: If a pull-up resistor is used for building a delay
time here (see Fig. 5–1 on page 89), referred to
the VDD pins, the maximum allowed value for
this resistor is 3.3 kOhm!
Fig. 4–16: Analog outputs OUTL(R) and connections
for filter capacitors FILTL(R)
+
AGNDC
−
1.25 V
VREF
Fig. 4–17: Analog ground generation with pin to
connect external capacitor
64
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
