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MAS3529F 参数 Datasheet PDF下载

MAS3529F图片预览
型号: MAS3529F
PDF下载: 下载PDF文件 查看货源
内容描述: MAS 35x9F MPEG 2/3层, AAC音频解码器, G.729附录编解码器 [MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec]
分类和应用: 解码器编解码器
文件页数/大小: 92 页 / 1187 K
品牌: MICRONAS [ MICRONAS ]
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MAS 35x9F  
DATA SHEET  
4.3. Pin Descriptions  
VSENS1/VSENS2  
IN  
Sense input and power output of DC/DC converters. If  
the respective DC/DC converter is not used, this pin  
should be connected to a supply to enable proper  
function of the PUP-signals.  
4.3.1. Power Supply Pins  
The use of all power supply pins is mandatory to  
achieve correct function of the MAS 35x9F.  
DCEN  
IN  
VDD, VSS  
Digital supply pins.  
SUPPLY  
SUPPLY  
SUPPLY  
Enable signal for both DC/DC converters. If none of  
the DC/DC converters is used, this pin must be con-  
nected to VSS.  
XVDD, XVSS  
Supply for digital output pins.  
PUP  
OUT  
Power-up. This signal is set when the required volt-  
ages are available at both DC/DC converter output  
pins VSENS1 and VSENS2. The signal is cleared  
when both voltages have dropped below the reset  
level in the DCCF Register.  
I2CVDD  
2
Supply for I C interface circuitry. This net uses VSS or  
XVSS as the ground return line.  
PVDD  
SUPPLY  
Auxiliary pin for analog circuitry. This pin has to be  
connected via a 3 nF capacitor to AVDD1. Extra care  
should be taken to achieve a low-inductance PCB line.  
VBAT  
IN  
Analog input for battery voltage supervision.  
AVDD0/AVSS0  
SUPPLY  
4.3.4. Oscillator Pins and Clocking  
Supply for analog output amplifier.  
XTI  
XTO  
IN  
OUT  
AVDD1/AVSS1  
SUPPLY  
Supply for internal analog circuits (A/D, D/A convert-  
ers, clock, PLL, S/PDIF input).  
The XTI pin is connected to the input of the internal  
crystal oscillator, the XTO pin to its output. Each pin  
should be directly connected to the crystal and to a  
ground-connected capacitor (see application diagram,  
Fig. 5–1 on page 89).  
AVDD0/AVSS0 and AVDD1/AVSS1 should receive the  
same supply voltages.  
CLKO  
OUT  
4.3.2. Analog Reference Pins  
The CLKO can drive an output clock line.  
AGNDC  
Internal analog reference voltage. This pin serves as  
the internal ground connection for the analog circuitry.  
4.3.5. Control Lines  
I2CC  
I2CD  
SCL  
SDA  
IN/OUT  
IN/OUT  
VREF  
2
Analog reference ground. All analog inputs and out-  
puts should drive their return currents using separate  
traces to a ground starpoint close to this pin. Connect  
to AVSS1. This reference pin should be as noise-free  
as possible.  
Standard I C control lines.  
DVS  
IN  
2
I C device address selector. Connect this pin either to  
2
2
VDD (I C device address: 3E/3F ) or VSS (I C  
device address: 3C/3D ) to select a proper I C  
hex  
2
hex  
device address (see also Table 3–2 on page 23).  
4.3.3. DC/DC Converters and  
Battery Voltage Supervision  
4.3.6. Parallel Interface Lines  
DCSG1/DCSG2  
SUPPLY  
DC/DC converters switch ground. Connect using sep-  
arate wide trace to negative pole of battery cell. Con-  
nect also to AVSS0/1 and VSS/XVSS, VREF.  
PI12..PI19  
IN/OUT  
The PIO input pins PI12..PI19 are used as 8-bit I/O  
interface to a microcontroller in order to transfer com-  
pressed and uncompressed data. PI12 is the LSB,  
PI19 the MSB.  
DCSO1/DCSO2  
SUPPLY  
DC/DC converter switch connection. If the respective  
DC/DC converter is not used, this pin must be left  
vacant.  
60  
June 30, 2004; 6251-505-1DS  
Micronas