MAS 35x9F
DATA SHEET
1.1. Features
Hardware Features
– Two independent embedded DC/DC converters,
(e.g., for DSP and flash RAM supply)
Firmware
– MPEG 1/2 layer 2 and layer 3 decoder
– Low DC/DC converter start-up voltage (0.9 V)
– DC converter efficiency up to 95%
– Battery voltage monitor
– Extension to MPEG 2 layer 3 for low sampling rates
(“MPEG 2.5”)
– Extraction of MPEG Ancillary Data
– Low supply voltage down to 2.2 V
– MPEG 2 AAC decoder (low-complexity profile)
– Low power dissipation, e.g., 87 mW
– Micronas G.729 Annex A speech compression and
decompression
(128kBit/s, 44.1 kHz, Headphone playback)
– High-performance RISC DSP core
– On-chip crystal oscillator
– Master or slave clock operation
– Adaptive bit rates (bit rate switching)
– Hardware power management and power-off func-
tions
– Intelligent power management (processor clock is
dependent on sampling frequencies)
– Microphone amplifier
– SDMI-compliant security technology
– Stereo channel mixer
– Stereo A/D converter for FM/AM-radio and speech
input
– Bass, treble, and loudness function
– Micronas Bass (MB)
– CD quality stereo D/A converter
– Headphone amplifier
– Automatic Volume Control (AVC)
– Noise and power-optimized volume
– External clock or crystal frequency of 13...28 MHz
– Standby current < 10 µA
Interfaces
– Two serial asynchronous interfaces for bit streams
and uncompressed digital audio
– Parallel handshake bit stream input
2
– Serial audio output via I S and related formats
– S/PDIF data input and output
2
– Controlling via I C interface
1.2. Features of the MAS 35x9F Family
Feature
3509
X
3519
X
3529
3539
3549 3559
Layer 3 Decoder
G.729 Encoder/Decoder
AAC Decoder
X
X
X
X
X
X
X
X
6
June 30, 2004; 6251-505-1DS
Micronas
MICRONAS [ MICRONAS ]
