PRELIMINARY DATA SHEET
MAS 3507D
Table 3–7: DC/DC-converter switch frequency (Bits 8,
Table 3–8: DC Converter Output Voltages (Bits
13..10 of DCCF-register)
16..14, Bit 9 of DCCF-register)
DCCF Value
(hex)1)
fSW
DCCF Value DC/DC
Internal
Voltage
(hex)1)
Converter
Output
Monitor 2)
Bit 8 = 0
Bit 8 = 1
0CC00
0C800
0C400
0C000
04C00
04800
04400
04000
01C00
01800
01400
01000
00C00
00800
00400
00000
156 kHz
160 kHz
163 kHz
167 kHz
171 kHz
175 kHz
179 kHz
184 kHz
188 kHz
194 kHz
199 kHz
204 kHz
210 kHz
216 kHz
223 kHz
230 kHz
238 kHz
245 kHz
253 kHz
263 kHz
272 kHz
283 kHz
295 kHz
307 kHz
320 kHz
335 kHz
351 kHz
368 kHz
387 kHz
409 kHz
433 kHz
460 kHz
1C000
18000
14000
10000
0C000
08000
04000
00000
1C200
18200
14200
10200
0C200
08200
04200
00200
3.5 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2,8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2,8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
1.9 V
1.8 V
1) All other bits are set to zero (DC/DC-converter
output voltage = 3.0 V)
1) All other bits are set to zero (fSW = 230 kHz)
2) PUP signal becomes inactive when output below
The DC/DC converter may generate interference noise
that could be unacceptable for some applications.
Thus the oscillator frequency may be adjusted in 16
steps in order to allow the system controller to select a
base frequency that does not interfere with an other
application.
The CLKI input provides the base clock fCKLI for the
frequency divider whose output is made symmetrical
with an additional divider by two. The divider quotient
is determined by the content of the DCCF register.
This register allows 32 settings generating a DC/DC
converter clock frequency fdc between:
fCKLI
-------------------------
=
fSW
2 (m + n)
n
{0, 15}, m {16, 32}
(EQ 3)
Micronas
27
MICRONAS [ MICRONAS ]
