MAS 3504D
4.2.1.5. Voltage Supervision And Other Functions
4.2.1.8. Miscellaneous
POR
CLKI
IN
IN
This is the clock input of the MAS 3504D. CLKI should
be a buffered output of a crystal oscillator. Standard
clock frequency is 18.432 MHz.
The Power On Reset pin is used to reset the digital
parts of the MAS 3504D. POR is a low active signal.
TE
IN
CLKO
OUT
The TE pin is for production test only and must be con-
nected with VSS in all applications.
This pin has no function.
PUP
OUT
4.2.2. Pin Configurations
The PUP output indicates that the power supply volt-
age exceeds its minimal level (software adjustable).
XVDD
XVSS
SID
PI8
WSEN
IN
SOC
SOI
SII
WSEN enables DSP operation and switches on the
DC/DC-converter.
SIC
SOD
PI4
PI12
WRDY
OUT
33 32 31 30 29 28 27 26 25 24 23
PI3 34
PI2 35
22 PI13
21 PI14
20 PI15
19 PI16
18 PI17
17 PI18
16 PI19
15 PCS
14 PR
WRDY has two functions depending on the state of the
WSEN signal.
PI1 36
PI0 37
If WSEN = ’0’, it indicates that a valid clock has been
recognized at the CLKI clock input.
CLKO 38
PUP 39
WSEN 40
WRDY 41
AVDD 42
CLKI 43
AVSS 44
MAS 3504D
If WSEN = ’1’, the WRDY output will be set to ‘0’ until
the internal clock synthesizer has locked to the incom-
ing audio data stream, and thus, the CLKO clock out-
put signal is valid.
13 VSENS
12 DCSO
1
2
3
4
5
6
7
8
9
10 11
4.2.1.6. Serial Input Interface
TE
DCSG
POR
I2CC
I2CD
VDD
RTW
RTR
EOD
DCEN
SID
SII
SIC
IN
IN
IN
VSS
Data, Frame Indication, and Clock line of the serial
input interface. The SII indicates whether the left or the
right audio sample is transmitted.
Fig. 4–3: PMQFP44 package
4.2.1.7. Serial Output Interface
SOD
SOI
SOC
OUT
OUT
OUT
Data, Frame Indication, and Clock line of the serial
output interface. The SOI indicates whether the left or
the right audio sample is transmitted.
26
Micronas
MICRONAS [ MICRONAS ]
