MAS 3504D
3.5.2.4. Pause and Mute
3.5.4.2. Input Configuration (Reg. 61hex)
If the pause bit is set, the processing continues until
the current page is finished and then en-/decoding is
paused. The pause mode lasts until the pause bit is
cleared again or the mode is set to 0.
The content of this register is set on startup by the
firmware. Additional to the Wordlength setting for the
serial interfaces, some other settings can be made.
If the mute bit is set, the output is muted immediately.
3.5.4.3. Output Configuration (Reg. E1hex)
Note that the other bits of the UserControl register
have to stay on their old values when switching to
pause mode.
The content of this register is set on startup by the
firmware. Additional to the Wordlength setting for the
serial interfaces, some other settings can be made.
3.5.3. Volume Control (Reg. FChex
)
3.5.5. Hardware Control (Reg. FAhex)
Volume control is implemented in the MAS 3504D. It
allows to adjust the output volume linear from 0hex
(silence) to 7FFFFhex (original volume).
The HWControl register is used to set special opera-
tion options.
If the page headers bit is 0, a header frame is trans-
ferred in front of each page of 50 data frames. If the
header bit is 1, all the frames are G.729 data frames.
3.5.4. Interface Control
All the interface control registers have to be written
before the encoder or decoder is started by writing to
the UserControl register. Otherwise they have no
effect until the operation mode is changed.
Bits 2 and 1 are used to select input channels for
encoding. If both bits are set to 0, the left and right
channel are added to get the mono input signal. If only
one of this bits is 1, only the corresponding channel is
used as input.
3.5.4.1. Wordlength Control (Reg. 74hex
)
A value of 0hex sets wordlength on SDI and SDO inter-
faces to 32 bit. 1hex sets wordlength to 16 bit.
page
header
100
page
header
frame frame
99
frame
101
page
header
frame frame frame
1
frame
49
frame
51
frame
102
frame
49
frame
52
...
...
...
2
3
10ms 10ms
...
...
byte byte byte byte byte
byte byte byte
byte byte
$64 $6d
$72
$64 $61 $74 $61
$f4 $01
$31
2
1
4
3
6
7
10
9
5
8
Fig. 3–2: Schematic timing of the data transmission with preceeding header
18
Micronas
MICRONAS [ MICRONAS ]
