HAL700, HAL740
2. Functional Description
Clock
DATA SHEET
The HAL700 and the HAL740 are monolithic inte-
grated circuits with two independent subblocks each
consisting of a Hall plate and the corresponding com-
parator. Each subblock independently switches the
comparator output in response to the magnetic field at
the location of the corresponding sensitive area. If a
magnetic field with flux lines perpendicular to the sen-
sitive area is present, the biased Hall plate generates a
Hall voltage proportional to this field. The Hall voltage
is compared with the actual threshold level in the com-
parator. The subblocks are designed to have closely
matched switching points. The output of comparator 1
attached to S1 controls the open drain output at Pin 3.
Pin 2 is set according to the state of comparator 2 con-
nected to S2.
The temperature-dependent bias – common to both
subblocks – increases the supply voltage of the Hall
plates and adjusts the switching points to the decreas-
ing induction of magnets at higher temperatures. If the
magnetic field exceeds the threshold levels, the com-
parator switches to the appropriate state. The built-in
hysteresis prevents oscillations of the outputs.
The magnetic offset caused by mechanical stress is
compensated for by use of “switching offset compen-
sation techniques”. Therefore, an internal oscillator
provides a two-phase clock to both subblocks. For
each subblock, the Hall voltage is sampled at the end
of the first phase. At the end of the second phase, both
sampled and actual Hall voltages are averaged and
compared with the actual switching point.
Shunt protection devices clamp voltage peaks at the
output pins and V
DD
-pin together with external series
resistors. Reverse current is limited at the V
DD
-pin by
an internal series resistor up to
−15
V. No external
reverse protection diode is needed at the V
DD
-pin for
reverse voltages ranging from 0 V to
−15
V.
signals are generated by the HAL700 and the
HAL740. The magnetic flux density at the locations of
the two Hall plates is shown by the two sinusodial
curves at the top of each diagram. The magnetic
switching points are depicted as dashed lines for each
Hall plate separately.
t
BS1
BS1
on
t
BS2
BS2
on
t
Pin 2
V
OH
V
OL
t
Pin 3
V
OH
V
OL
t
I
DD
1/f
osc
t
f
t
f
t
Fig. 2–1:
HAL700 timing diagram with respect to the
clock phase
6
Nov. 30, 2009; DSH000029_002EN
Micronas
MICRONAS [ MICRONAS ]
