13.5/16 MHz
Scaler
27/32 MHz
40.5/40.0 MHz
dig. Bright.
digital/analog
Scan.
Vel. Mod.
SVM
DAC
Contrast
FI-
FO
Scaler
2
Y
FI-
Y
Peaking
Y
R,G,B
digital
RGB
Matrix
1
FO
Soft Limiter
R,G,B
Cr
Cr
CrCb
4:2:2/4:1:1
FI-
FO
Scaler
1
Scaler
2
CTI
Intpl.
4:2:2
Intpl.
4:4:4
FI-
FO
Satu-
Picture
Frame
Gen.
ration
Cb
White-Dr.
BCL
Cb
×
Line-locked
Clock
27/32 MHz
Cock
Generator
3
×DAC
RGB
DAC
cutoff
DAC
black
H & V
Timing
FIFO
Read Ctrl
3×DAC
R,G,B
int. H/V
Display
Frequency
Doubling
int. Bright.
×White-Drive
H / V
RGB
out
FIFO
Write Ctrl
XDFP
3
×
DAC
ext. Bright.
White-Drive
– H-PLL2/3, flyback control
and soft start/stop
– vertical, E/W deflection
with EHT compensation
and vertical zoom
FBL1/2
in
FBL
Prio
×
I2C
Inter-
face
R,G,B
SDA/
SCL
RGB1
in
– beam current limiter
– cutoff & drive control loop
Clamp-
ing
3×DAC
ext. Contr.
2
×
DAC
Measu-
rement
ADC
×
White-drive
RGB2
in
Clk
Security
H/V
Protection
H-Drive
Gen.
H-Flyb.
Skew
Clamp-
ing
5 MHz
CLK
×
BCL
V, E/W
HDrive
H/V Prot.
H-Flyb
V & E/W Sense RSW1&2
Fig. 2–7: Detailed block diagram of the DDP 3310B
MICRONAS [ MICRONAS ]
