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CAP3001A 参数 Datasheet PDF下载

CAP3001A图片预览
型号: CAP3001A
PDF下载: 下载PDF文件 查看货源
内容描述: 汽车音响处理器硬件 [Car Audio Processor Hardware]
分类和应用: 汽车音响
文件页数/大小: 37 页 / 461 K
品牌: MICRONAS [ MICRONAS ]
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CAP 3001 A
Car Audio Processor
1. Introduction
The CAP 3001 A Car Audio Processor presents the one-
chip solution for a highly integrated car radio concept. It
is housed in a 68-pin Plastic Leaded Chip Carrier Pack-
age.
The CAP 3001 A Car Audio Processor is a new CMOS
processor to be used for car radio systems.
The application consists essentially of the following
components:
– conventional FM tuner, FM–IF stage and FM demodu-
lation
– conventional AM tuner and IF stage
– Car Audio Processor CAP 3001 A
– microcontroller
– analog audio sources
– digital audio source
1.1. Features
1)
– stereo decoder
– baseband audio processing
– ignition noise canceller
– synthesizer with fast tuning
– AM tuning for 450 to 460 kHz or 10.7 MHz IF
– AM IF processing (450 to 460 kHz)
– AM stereo (C-QUAM) demodulation
– ARI/RDS processing
– PDAI Programmable Digital Audio Interface
– A/D converter
– D/A converter with eightfold oversampling filter.
In the analog part various input switches, A/D converters
and D/A converters are combined. Five A/D converters
handle the conversion of analog signals into digital sig-
nals. Two of these are specially designed for high quali-
ty, one in particular for the conversion of an independent
signal path for ARI/RDS signals and the remaining two
to be used for the evaluation of analog signals of a lower
quality standard (information on field strength and infor-
mation from potentiometers). Two D/A converters, each
equipped with an eightfold oversampling filter, generate
analog output signals. These two outputs can be split up
and distributed via four independently adjustable vol-
ume control switches into four output stages.
2. Functional Description
2.1. Architecture
The architecture of the CAP 3001 A processor com-
prises three main function blocks:
2.1.1. DSP Block
The DSP block consists of a “General Purpose16-Bit
Digital Signal Processor” which handles 24 million in-
structions per second. The data word length is 16 bits
and the hardware multiplier operates with an initial word
length of 16@10 with a 20-bit result. The memory covers
256@16)256@10 bit RAM and 2 k instruction ROM.
2.1.2. Digital Part
A main portion consists of hardwired digital filters, such
as decimation filters for the A/D converters and interpo-
lation filters for D/A converters. The modulators for ARI/
RDS and pilot tone, as well as the complete circuitry for
the ignition noise canceller are realized digitally. The log-
ical conclusion for a higher integration is the incorpora-
tion of the synthesizer for AM and FM tuning into this
hardware block. Naturally the customary serial inter-
faces for digital audio signals are also included.
2.1.3. Analog Part
4
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