128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Read Operations
WAIT Operation
WAIT indicates the validity of output data during synchronous READ operations. It is
asserted when output data is invalid and de-asserted when output data is valid. WAIT
changes state only on valid clock edges. Upon power-up or exit from reset, WAIT de-
faults to LOW true (RCR[10] = 0).
WAIT is de-asserted during asynchronous reads. During WRITE operations, WAIT is
High-Z on non-mux devices, and deasserted on AD-mux devices.
Table 18: WAIT Behavior Summary – Non-MUX
Device Operation
Standby (Device not selected)
Output Disable
CE#
HIGH
LOW
LOW
OE#
X
WE#
X
WAIT
High-Z
High-Z
HIGH
LOW
HIGH
HIGH
Synchronous Read
Active
WAIT asserted = invalid data
WAIT de-asserted = valid data
Asynchronous Read
Write
LOW
LOW
LOW
HIGH
HIGH
LOW
De-asserted
High-Z
1. This table does not apply to AADM devices. See AADM Mode for WAIT behavior in
AADM mode.
Note:
Table 19: WAIT Behavior Summary – AD MUX
Device Operation
Standby (Device not selected)
Output Disable
CE#
HIGH
LOW
LOW
OE#
X
WE#
X
WAIT
High-Z
HIGH
LOW
HIGH
HIGH
De-asserted
Synchronous Read
Active
WAIT asserted = invalid data
WAIT de-asserted = valid data
Asynchronous Read
Write
LOW
LOW
LOW
HIGH
HIGH
LOW
De-asserted
De-asserted
1. This table does not apply to AADM devices. See AADM Mode for WAIT behavior in
AADM mode.
Note:
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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