P30-65nm
Appendix C Revision History
Date
Revision Description
Jan 2008
01
Initial release.
Add Top/Bottom device information such as memory map, device ID, CFI, ordering information etc.
Add 40Mhz specification for TSOP package.
Add a Note to clarify the SR output after E8 command in “Buffered Programming” on
page 24.
Align flowchart of Program/Erase Suspend as same as 130nm.
Align flowchart of block locking operation as same as 130nm.
Add note 7 to flowchart of Buffer program.
Aug 2009
02
Update Ordering Information.
Update RCR.7 in “Read Configuration Register Description” on page 35.
Add 2-Gbit density related information such as memory map, CFI, ordering information, 2G DC
current spec, capacitance, dual-die configuration and Device ID note etc.
Update suspend latency spec.
Nov 2009
Feb 2010
03
04
Update on TSOP package with VCCQ and Temp.
Update the erase and program performance.
Ordering information with Device feature digit.
Add 2 RC part in valid combination.
CFI update aligned with performance update.
Update the ADV# signal connection for TSOP package.
Add comments for synchronous page mode and synchronous mode read.
Burst latency count update in Table 14, “LC and Frequency Support” on page 37.
BEFP setup time update from 5 to 20.
Apr 2010
05
Update 2-Gbit Tacc time 95ns.
Sept 2012
06
Corrected tCHQV from 22ns to 17ns.
Datasheet
86
Sept 2012
Order Number: 208042-06
MICRON [ MICRON TECHNOLOGY ]
