512Mb, 1Gb, 2Gb: P30-65nm
AC Write Specifications
Figure 37: Write to Synchronous Read Timing
Latency count
tVLCH
tAVCH
tAVQV
CLK
tAVWH
tWHAX
tCHAX
tVHAX
A
tVLVH
ADV#
tELWL
tWHEH
tEHEL tELCH
CE#
tWHAV
tWHCH/L
tWHVH
tWLWH
WE#
OE#
tGLQV
tGLTX
tELQV
tCHTV
WAIT
tCHQV
tCHQX
tCHQV
tDVWH
tWHDX
DQ
D
Q
Q
tPHWL
RST#
1. WAIT shown de-asserted and High-Z per OE# de-assertion during WRITE operation
(RCR10 = 0, WAIT asserted LOW).
Note:
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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