Operating features
Table 2.
N25Q128 - 1.8 V
Device Status after Reset Low Pulse
Conditions:
reset pulse occurred
Lock bits
status
Internal logic status
Addressed data
While decoding an instruction(1): WREN, WRDI,
RDID, RDSR, READ, RDLR, Fast_Read, DOFR,
DIOFR, QOFR, QIOFR, WRLR, PW, PP, PE, SE,
BE, SSE, DP, RDP
Reset to 0
Reset to 0
Same as POR (2)
Not significant
Addressed data
could be
modified
Under completion of an Erase or Program cycle of
a PW, PP, DIFP, DIEFP, SSE, SE, BE operation
Equivalent to POR (2)
Equivalent to POR
(after tW)
Write is correctly
completed
Under completion of a WRSR operation
Reset to 0
Reset to 0
Device deselected (S High) and in standby mode
Same as POR (2)
Not significant
Note:
1
2
S remains Low while Reset is Low.
See 11: Power-up and power-down
The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O
(DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP.
The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.
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