64Mb : x4, x8, x16
SDRAM
1
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9, A11
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
t
AS
AH
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
A10
t
AS
BA0, BA1
BANK 0
BANK 0
BANK 3
BANK 3
BANK 0
t
t
t
t
t
AC
AC
AC
AC
AC
t
t
t
t
t
t
OH
AC
OH
OH
OH
OH
DOUT
m
DOUT m + 1
DOUT m + 2
DOUT m + 3
DOUT b
DQ
t
LZ
t
t
t
RP - BANK 0
RCD - BANK 0
CAS Latency - BANK 0
RCD - BANK 0
t
t
RAS - BANK 0
RC - BANK 0
t
t
RCD - BANK 3
CAS Latency - BANK 3
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AC(3)
AC(2)
AH
5.5
–
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
LZ
1
1.5
1
0.8
1.5
1
0.8
1.5
1
1
2
1
3
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
1.5
2.5
2.5
6
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
AS
OH
2
3
3
CH
3
RAS
RC
42 120,000 37 120,000 44 120,000 50 120,000 ns
CL
3
60
18
18
12
60
15
15
14
66
20
20
15
70
20
20
20
ns
ns
ns
ns
CK(3)
CK(2)
CKH
CKS
8
RCD
RP
–
7.5
0.8
1.5
10
1
1
0.8
1.5
RRD
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
45
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