64Mb : x4, x8, x16
SDRAM
1
SINGLE READ – WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
t
CKS CKH
t
CMS CMH
2
2
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
ACTIVE
NOP
NOP
t
t
CMS
CMH
DQM /
DQML, DQMU
t
t
AH
AS
3
A0-A9, A11
ROW
ROW
COLUMN m
t
t
t
AS
AH
AH
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
BA0, BA1
BANK
BANK
BANK
t
AC
t
OH
DOUT
m
DQ
t
CAS Latency
t
RCD
HZ
t
t
t
RP
RAS
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AC(3)
AC(2)
AH
5.5
–
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
1
0.8
1.5
0.8
1.5
1
2
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1.5
1
1.5
2.5
2.5
6
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.5
–
5.4
5.4
5.4
6
6
6
AS
CH
3
1
2
1
3
1
3
1
3
CL
3
OH
CK(3)
CK(2)
CKH
CKS
8
RAS
RC
42 120,000 37 120,000 44 120,000 50 120,000 ns
–
7.5
0.8
1.5
10
1
60
18
18
60
15
15
66
20
20
70
20
20
ns
ns
ns
1
0.8
1.5
RCD
RP
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
t
2. READ command not allowed or RAS would be violated.
3. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
44
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