64Mb : x4, x8, x16
SDRAM
SELF REFRESH MODE
T0
T1
T2
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
CLK
CKE
( (
) )
t
( (
) )
t
CK
CH
t
CKS
RAS(MIN)1
t
≥
( (
) )
( (
) )
( (
) )
t
t
CKS CKH
t
t
CMS
CMH
( (
) )
( (
) )
AUTO
REFRESH
or COMMAND
INHIBIT
AUTO
REFRESH
COMMAND
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
DQM/
DQML, DQMH
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11
A10
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
( (
) )
( (
) )
High-Z
( (
) )
( (
) )
2
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-6
-7 E
-7 5
-8 E
-6
-7 E
-7 5
-8 E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
AH
1
0.8
1.5
2.5
2.5
7
0.8
1.5
1
ns
ns
CKS
CMH
CMS
RAS
RP
1.5
1
1.5
0.8
1.5
1.5
0.8
1.5
2
1
2
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
1.5
2.5
2.5
6
2
3
3
8
CH
2.5
2.5
7.5
10
ns
ns
ns
ns
ns
1.5
CL
42 120,000 37 120,000 44 120,000 50 120,000 ns
CK(3)
CK(2)
CKH
18
70
15
67
20
75
20
80
ns
ns
–
7.5
0.8
10
1
XSR
1
0.8
*CAS latency indicated in parentheses.
t
NOTES: 1. No maximum time limit for Self Refresh mode. RAS(MAX) applies to non-Self Refresh mode.
t
2. XSR requires minimum of two clocks regardless of frequency and timing.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
40
MICRON [ MICRON TECHNOLOGY ]
