128Mb: x4, x8, x16
SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
SYNCHRONOUS
DRAM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
x16 x8 x4
-
-
-
-
V
DQ0
DD
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7 NC
NC DQ0
DQ15
VssQ
DQ14
DQ13
-
NC
DQ6 DQ3
-
NC
DQ5 NC
-
NC
DQ4 DQ2
-
NC
-
NC
-
NC
DQ0 DQ1
-
NC
NC DQ2
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
-
NC
-
NC
VDDQ
DQ12
DQ11
VssQ
DQ10
DQ9
VDDQ
DQ8
Vss
-
NC
-
NC
-
V
DD
Q
9
• LVTTL-compatible inputs and outputs
• Single +3.3V 0.3V power supply
NC DQ5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ1 DQ3 DQ6
-
-
NC
-
-
NC
-
-
VssQ
NC
-
NC DQ7
OPTIONS
• Configurations
MARKING
-
VDD
-
-
NC
-
NC DQML
NC
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
DQMH DQM DQM
-
-
-
-
-
-
-
-
-
-
-
-
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
32M4
16M8
8M16
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
• WRITE Recovery (tWR)
-
tWR = “2 CLK”1
A2
-
-
• Package/Pinout
-
-
Plastic Package – OCPL2
54-pin TSOP II (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
DD
-
TG
FB 3,6
FC 3,6
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4 16 Meg x 8 8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
-8E 3,4,5
-75
-7E
Configuration
Refresh Count
Row Addressing
Bank Addressing
4K
4K
4K
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
• Self Refresh
Standard
Column Addressing 2K (A0–A9, A11)
None
L
Low power
KEY TIMING PARAMETERS
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
None
IT 3
SPEED
CLOCK
ACCESS TIME SETUP HOLD
GRADE FREQUENCY CL = 2* CL = 3* TIME
TIME
Part Number Example:
-7E
-7E
-75
-8E3,4,5
-75
-8E3 ,4,5
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
–
5.4ns
–
–
6ns
6ns
5.4ns
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
MT48LC16M8A2TG-7E
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
–
5.4ns
6ns
–
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatability.
–
6. See page 59 for FBGA Device Marking Table.
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MICRON [ MICRON TECHNOLOGY ]
